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研究生:劉彥岑
研究生(外文):Yan-Cen Liou
論文名稱:無線電容耦合電路之自我測試及靈敏度優化
論文名稱(外文):The Study of Self - Test and Sensitivity Analysis of Capacitance Coupling Interconnect Circuit
指導教授:黃有榕
指導教授(外文):Yu-Jung Huang
學位類別:碩士
校院名稱:義守大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:中文
論文頁數:156
中文關鍵詞:交流電容式耦合互聯三維積體電路堆疊晶片傳輸
外文關鍵詞:AC capacitive coupling interconnect3-D ICchip-to-chip communication
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本篇論文主要研究三維積體電路無線電容式耦合傳輸電路之電路特性,並提出電容式耦合傳輸電路的自我測試方法。主要探討無線電容式耦合傳輸電路的各項影響因素,以TSMC 90nm製程規格之電路,利用電路模擬軟體HSPICE,探討電路中耦合電容、寄生電容對電路訊號造成的影響,並且通過調整接收器電路中的訊號放大器之導通電壓提升訊號的靈敏性,使訊號更加優良,並且考慮實際製程時產生的變異情況,對FF、FS、TT、SF、SS此5種Corner Case分析電路狀況,探討電路之實用性。此外針對耦合傳輸電路進行測試,模擬測試電路的高速訊號反應以及在亂數訊號時之電路狀態,並提出分別在傳送器以及接收器晶片設置自我測試之方法,使單晶片可獨立自我測試,減少實體產品測試晶片的困難度。
This thesis is focused on the study of the circuit characteristics of the wireless capacitive coupling transmission circuit, and the test method of the capacitive coupling transmission circuit. The proposed circuit is simulated using HSPICE simulator based on TSMC 90nm process specifications. The effects of circuit transmission signal due to circuit coupling capacitance and parasitic capacitance are investigated. By adjusting the feedback bias of the received signal, the sensitivity of the signal is enhanced to improve the signal quality. The comparison for the circuit performance for FF, FS, TT, SF, SS five process corner is also demonstrated. A self-test methodology with a complete capacitive coupled serial link for a fully differential pulse receiver design is demonstrated in this study. The simulation results indicated the proposed circuit with the self-test characteristics can achieve differential signal transmission for 3D stacked dies up to 4 Gbps.
中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 xvii
第一章 緒論1
1-1-1研究動機 1
1-1-2研究方法 2
1-2-1自我測試電路 3
1-2-2自我測試電路 3
第二章 背景簡介5
2-1電容式耦合 5
2-2差分訊號 6
2-3眼圖分析 8
第三章 無線電容耦合之自我測試及敏感度優化 12
3-1電路架構 12
3-2電路詳細說明 14
3-2-1傳送器電路 14
3-2-2接收器電路 16
3-2-3傳送器自我測試電路 18
3-2-4接收器自我測試電路 20
第四章 電容效應分析 22
4-1-1耦合電容之影響 22
4-1-2傳送端電路寄生電容之影響 28
4-1-3接收端電路寄生電容之影響 32
4-1-4耦合電容與寄生電容互相之影響 36
4-1-5耦合電容之設計 41
4-2靈敏性電路 42
4-3耦合電容之設計 50
第五章 2G訊號靈敏性電路 54
5-1傳送器寄生電容分析 54
5-2接收端寄生電容分析 57
5-3兩端寄生電容階篇大隻分析 60
5-4耦合效應 63
5-5放大器導通電壓補強耦合效應不佳時的狀況 66
5-4製程變異 69
第六章 電路測試 89
6-1高速訊號測試 89
6-2高速訊號測試 96
6-2-1Pad結構 96
6-2-2傳送端自我測試電路模擬分析 98
6-2-3接收端自我測試電路模擬分析 103
6-3亂數輸入訊號測試 108
第七章 結論 110
參考文獻 111
附錄 115
附錄A 115
附錄B 122
附錄C 133
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