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研究生:黃億泰
研究生(外文):I-TAI Huang
論文名稱:應用基因演算法於複雜環境下進行分數階PID控制器之最佳化干擾斥拒設計
論文名稱(外文):Optimal Fractional Order PID Controller Design for Disturbance Rejection Using Genetic Algorithm Under the Complex Environments
指導教授:李慶祥李慶祥引用關係
指導教授(外文):Ching-Hsiang Lee
口試委員:凃文福李宗恩
口試委員(外文):Wen-Fu TuZong-En Lee
口試日期:2017-07-14
學位類別:碩士
校院名稱:國立高雄應用科技大學
系所名稱:電機工程系博碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:中文
論文頁數:62
中文關鍵詞:分數階PID控制器基因演算法SISO系統時間延遲系統
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本論文利用分數階PID控制器之高階等效傳輸函數之性質,來近似複雜環境下之外在干擾的數學模型,並利用基因演算法設計分數階PID控制器之參數,以同時完成閉路系統的穩定性和近似的強健追蹤。文中分別對下列二種系統設計分數階PID控制器,以完成未知干擾之斥拒: (1) 單輸入單輸出系統 (2) 單輸入單輸出時間延遲系統。本文除了運用基因演算法之適應函數設計單輸入單輸出系統之分數階PID控制器外,也設計單輸入單輸出時間延遲系統之分數階PID控制器。最後透過Matlab數值模擬,分別探討分數階PID控制器對單輸入單輸出系統、單輸入單輸出時間延遲系統之控制性能並與參考文獻所設計之控制器作比較,以驗證本論文所提出之設計方法之有效性以及優異性。
This paper exploits the ability of approximating the high order transfer function of a fractional order PID controller, and searches the optimal parameters of the fractional order PID controller using genetic algorithm to solve the robust disturbance rejection problem . In this paper, two different kinds of systems are considered: (1) Single-input single-output system, (2) Single-input single-output time-delay system. A suitable class of fitness functions for genetic algorithm are selected in this paper to design fractional order PID controller for single-input single-output system, and Single-input single-output time-delay system. Then, the numerical simulation using Matlab software is proceeded to investigate the performance of the two different kind of systems and to verify the validity of the proposed methods in this paper.
摘要
Abstract
致謝
目錄
表目錄
圖目錄
第一章、 緒論
1.1 研究動機與文獻回顧
1.2 論文綱要
第二章、預備知識
2.1 干擾斥拒
2.1.1 零誤差的基本原理與內部模型法則
2.1.2 分數階PID控制器
2.2 分數階微積分
2.2.1 分數階微積分定義 Grunwald-Letnikov (G-L)
2.2.3 分數階微積分定義 Caputo
2.3 分數階系統
2.3.1 分數階拉普拉斯轉換
2.3.2 分數階微分方程
2.4 時間延遲系統
2.5 PID控制器
2.5.1 PI、PD、PID控制器優缺點介紹
2.6 分數階PID控制器
第三章、基因演算法與利用基因演算法設計分數階PID控制器
3.1 基因演算法
3.2 編碼及解碼
3.3 複製
3.4 交配
3.5 突變
3.6 適應函數
3.7 基因演算法設計流程圖
3.8 基因演算法設計分數階PID控制器
3.8.1 適應函數介紹
3.8.2 適應函數選擇
第四章、數值模擬
例題1: 單輸入單輸出系統
例題2: 一階單輸入單輸出時間延遲系統
例題3: 二階單輸入單輸出系統
例題4: 二階單輸入單輸出時間延遲系統
第五章、結論
參考文獻
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