跳到主要內容

臺灣博碩士論文加值系統

(18.97.14.91) 您好!臺灣時間:2025/01/16 20:03
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:徐萱齡
研究生(外文):Hsuan-Ling Hsu
論文名稱:熱處理溫度對電鍍銅/錫界面反應之影響
論文名稱(外文):Effect of thermal aging temperature on the interfacial reactions between electroplated Cu and Sn
指導教授:陳志銘陳志銘引用關係
指導教授(外文):Chih-Ming Chen
口試委員:顏怡文何政恩林慶炫
口試日期:2017-07-05
學位類別:碩士
校院名稱:國立中興大學
系所名稱:化學工程學系所
學門:工程學門
學類:化學工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:中文
論文頁數:78
中文關鍵詞:電鍍銅添加劑溫度界面反應可靠度
外文關鍵詞:Electroplated copperAdditivesTemperatureInterfacial reactionReliability
相關次數:
  • 被引用被引用:0
  • 點閱點閱:602
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
隨著科技日益進步,微電子產品更脫離不開微型化的發展,因此銲接點也會跟著縮小。目前半導體產業中接點可靠性疑慮已經成為不可避免的問題,像是銲接點金屬相互反應生成脆性介金屬化合物(Intermetallic compound, IMC),使得機械強度下降,此外,使用時流經銲點電流密度迅速增加,接點不僅僅會受到電遷移效應之影響,其中銲接點會因電流而生成熱能,這表示接點也會受到熱效應之衝擊,在長時間下因溫度可能使銲接點之性質產生變化,也是對電子產品使用壽命的疑慮之一。
電鍍技術通常使用於製造銅金屬化線路以作為與銲料的接點,而根據先前許多研究表示,銅電鍍過程裡溶液中的添加劑會產生一些有機雜質,進而在電鍍過程中可能被摻入沉積銅層中,金屬和銲料反應下,經過熱老化過程,在高溫時銲料與銅反應之界面處會誘發嚴重的孔洞生成,這會導致接點受到破壞的機率提升,因此本研究將會探討電鍍添加劑對電鍍銅的性質之影響,並且針對微電子產品在實際應用下所受到之不同溫度影響做模擬實驗,以觀察溫度對銲料與電鍍銅之界面反應,再更一步討論其對接點可靠度的影響。
本研究發現全部銅電鍍配方經Cu/Sn熱處理反應,溫度越高IMC成長越快,低溫則反應生成厚度及形狀不均,而CS(Cl-+SPS),PCS(PEG+Cl-+SPS),Cu foil三者界面均無孔洞,但是PC(PEG+Cl-)配方在低溫其IMC容易脆裂,而在高溫或長時間下不僅僅IMC成長厚度增加,還會有多層結構產生。動力學分析發現高溫下越接近體積擴散,四點探針偵測CS有最低電阻率。在推球實驗中, PC經過低溫熱處理後的機械強度最弱,此結果可經過聚焦型離子束(FIB)發現在低溫熱處理的Cu3Sn/Cu之間累積相當多孔洞而驗證,此外高溫則是發現孔洞分布位置在IMC內部及界面處,且孔洞周圍佈滿灰黑色物質。從二次離子質譜儀(SIMS)之雜質濃度分析結果得到各溫度下雜質濃度相對較高。熱處理越高溫,Cu6Sn5晶粒越大,而只有PC配方的Cu6Sn5上分布許多voids,分析發現是由三氯苯氣體所誘發。
Nowadays, development of microelectronic products follows the trend of miniaturization with the progress of technology. Therefore, the size of the solder joints shrinks and the reliability issue can not be avoided in semiconductor industry. One main reliability issue is the joint structure due to the formation of brittle intermetallic compounds (IMCs) resulting from the solder/metallization reactions. Also, the current density through the solder joints increases rapidly. The joints are not only affected by electromigration but also attacked by the thermal effect caused by current.
The electroplating technique is commonly used in fabricating the Cu metallization in the solder joints. Previous studies indicated that some impurities originated from the additives of electroplating solution. The impurities were incorporated in the Cu deposit and caused severe void formation at the solder/Cu interface during thermal aging. In this study, we investigate the effect of additives on the properties of electroplated copper. Moreover, the solder/electroplated copper interfacial reaction was observed and the reliability of solder joints was discussed.
The IMCs of the Cu/Sn reaction for all copper electroplating formulas grow at a faster rate at higher temperatures during thermal aging. The Sn/Cu interfaces prepared with CS (Cl-+SPS), PCS (PEG+Cl-+SPS), Cu foil are void-free. We find the IMCs formed at the Sn/Cu interface prepared with PC (PEG+Cl-) will easily break at low temperature and exhibit a multi-layer structure at high temperature. Kinetic analysis indicates the bulk-diffusion at high temperature. The four-point probe measurement shows that the Cu deposit prepared by the CS formula has the lowest resistivity.
Focused Ion Beam system (FIB) images show the voids accumulated at the Cu/Cu3Sn interface at low-temperature heat treatment which means that the mechanical strength of the joint prepared by the PC formula is the weakest at low temperature aging. Conversely, the voids distribute in IMC and interface at high temperature and the gray-dark substance appears around the periphery of the voids. Time-of-Flight Secondary Ion Mass Spectrometer (TOF-SIMS) results show the impurity concentration is similar.
摘要 i
Abstract ii
目錄 iv
圖目錄 vi
表目錄 x
第1章、緒論 1
第2章、文獻回顧 2
2.1為何使用電鍍銅 2
2.2電鍍添加劑在電鍍上之應用 4
2.3電鍍添加劑和雜質殘留之影響 9
2.4電鍍添加劑對銅/銲料反應之影響 17
2.5擴散機制 29
2.6溫度對電鍍銅/銲料反應之影響 32
2.7溫度對電鍍銅/銲料接點可靠度之影響 36
第3章、實驗方法 41
3.1 電鍍銅製備 41
3.2 電鍍銅/錫樣品製備 42
3.3 電鍍銅/錫之固/固反應 42
3.4 固/固反應界面分析 43
3.5 電鍍銅/錫接點機械強度測試 43
3.6 電鍍銅電性分析 44
3.7 電鍍銅雜質分析 44
3.8 氣相層析質譜儀分析 44
第4章、結果與討論 46
4.1 不同溫度下純銅/錫之固/固反應 46
4.2 不同溫度下不同添加劑之電鍍銅/錫之固/固反應 47
4.3不同溫度下之不同電鍍銅/錫介金屬化合物成長趨勢 53
4.4不同添加劑之電鍍銅電性分析 55
4.5不同溫度下之不同電鍍銅/錫接點機械強度測試 56
4.6不同溫度下電鍍銅/錫之固/固反應孔洞之分布情況 59
4.7不同溫度下之不同電鍍銅雜質分佈 63
4.8不同溫度下之不同電鍍銅/錫反應之Cu6Sn5表面型態 64
4.9電鍍PC配方之Cu6Sn5上孔洞形成原因分析 66
第5章、結論 71
第6章、參考文獻 73
[1]C. K. Hu, R. Rosenberg, and K. Y. Lee, "Electromigration path in Cu thin-film lines," Applied Physics Letters, Vol. 74, pp. 2945-2947 (1999).
[2]S. H. Brongersma, E. Kerr, I. Vervoort, A. Saerens, and K. Maex, "Grain growth, stress, and impurities in electroplated copper," Journal of Materials Research, Vol. 17, pp. 582-589 (2002).
[3]K. N. Chen, A. Fan, C. S. Tan, R. Reif, and C. Y. Wen, "Microstructure evolution and abnormal grain growth during copper wafer bonding," Applied Physics Letters, Vol. 81, pp. 3774-3776 (2002).
[4]J. Neuner, I. Zienert, A. Peeva, A. Preuße, P. Kücher, and J. W. Bartha, "Microstructure in copper interconnects–Influence of plating additive concentration," Microelectronic Engineering, Vol. 87, pp. 254-257 (2010).
[5]T. C. Liu, C. M. Liu, Y. S. Huang, C. Chen, and K. N. Tu, "Eliminate Kirkendall voids in solder reactions on nanotwinned copper," Scripta Materialia, Vol. 68, pp. 241-244 (2013).
[6]Y. S. Huang, C. M. Liu, W. L. Chiu, and C. Chen, "Grain growth in electroplated (111)-oriented nanotwinned Cu," Scripta Materialia, Vol. 89, pp. 5-8 (2014).
[7]C. M. Liu, H. W. Lin, Y. S. Huang, Y. C. Chu, C. Chen, D. R. Lyu, K. N. Chen, and K. N. Tu, "Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces of nanotwinned Cu," Scientific Reports, Vol. 5, pp. 9734 (2015).
[8]K. N. Tu, "Reliability challenges in 3D IC packaging technology," Microelectronics Reliability, Vol. 51, pp. 517-523 (2011).
[9]P. Dixit, C. W. Tan, L. Xu, N. Lin, J. Miao, J. H. L. Pang, P. Backus, and R. Preisser, "Fabrication and characterization of fine pitch on-chip copper interconnects for advanced wafer level packaging by a high aspect ratio through AZ9260 resist electroplating," Journal of Micromechanics and Microengineering, Vol. 17, pp. 1078 (2007).
[10]C. Gu, H. Xu, and T. Y. Zhang, "Fabrication of high aspect ratio through-wafer copper interconnects by reverse pulse electroplating," Journal of Micromechanics and Microengineering, Vol. 19, pp. 065011 (2009).
[11]N. T. Nguyen, E. Boellaard, N. P. Pham, V. G. Kutchoukov, G. Craciun, and P. M. Sarro, "Through-wafer copper electroplating for three-dimensional interconnects," Journal of Micromechanics and Microengineering, Vol. 12, pp. 395 (2002).
[12]H. Wang, P. Cheng, H. Wang, R. Liu, L. Sun, Q. Rao, Z. Wang, T. Gu, and G. Ding, "Effect of current density on microstructure and mechanical property of Cu micro-cylinders electrodeposited in through silicon vias," Materials Characterization, Vol. 109, pp. 164-172 (2015).
[13]A. Chrzanowska and R. Mroczka, "Influence of chloride anions and polyethylene glycol on the morphology of electrodeposited copper layers," Electrochimica Acta, Vol. 78, pp. 316-323 (2012).
[14]A. Chrzanowska, R. Mroczka, and M. Florek, "Effect of interaction between dodecyltrimethylammonium chloride (DTAC) and bis (3-sulphopropyl) disulphide (SPS) on the morphology of electrodeposited copper," Electrochimica Acta, Vol. 106, pp. 49-62 (2013).
[15]E. Shinada, T. Nagoshi, T. F. M. Chang, and M. Sone, "Crystallographic study on self-annealing of electroplated copper at room temperature," Materials Science in Semiconductor Processing, Vol. 16, pp. 633-639 (2013).
[16]S. Lagrange, S. H. Brongersma, M. Judelewicz, A. Saerens, I. Vervoort, E. Richard, R. Palmans, and K. Maex, "Self-annealing characterization of electroplated copper films," Microelectronic Engineering, Vol. 50, pp. 449-457 (2000).
[17]K. B. Yin, Y. D. Xia, C. Y. Chan, W. Q. Zhang, Q. J. Wang, X. N. Zhao, A. D. Li, Z. G. Liu, M. W. Bayes, and K. W. Yee, "The kinetics and mechanism of room-temperature microstructural evolution in electroplated copper foils," Scripta Materialia, Vol. 58, pp. 65-68 (2008).
[18]J. M. Paik, Y. J. Park, M. S. Yoon, J. H. Lee, and Y. C. Joo, "Anisotropy of grain boundary energies as cause of abnormal grain growth in electroplated copper films," Scripta Materialia, Vol. 48, pp. 683-688 (2003).
[19]S. P. Hau-Riege and C. V. Thompson, "In situ transmission electron microscope studies of the kinetics of abnormal grain growth in electroplated copper films," Applied Physics Letters, Vol. 76, pp. 309-311 (2000).
[20]M. Moriyama, K. Matsunaga, T. Morita, S. Tsukimoto, and M. Murakami, "The effect of strain distribution on abnormal grain growth in Cu thin films," Materials Transactions, Vol. 45, pp. 3033-3038 (2004).
[21]Q. Huang, A. Avekians, S. Ahmed, C. Parks, B. Baker-O'Neal, S. Kitayaporn, A. Sahin, Y. Sun, and T. Cheng, "Impurities in the electroplated sub-50 nm Cu lines: The effects of the plating additives," Journal of The Electrochemical Society, Vol. 161, pp. D388-D394 (2014).
[22]M. Kang and A. A. Gewirth, "Influence of additives on copper electrodeposition on physical vapor deposited (PVD) copper substrates," Journal of The Electrochemical Society, Vol. 150, pp. C426-C434 (2003).
[23]W. P. Dow, M. Y. Yen, W. B. Lin, and S. W. Ho, "Influence of molecular weight of polyethylene glycol on microvia filling by copper electroplating," Journal of The Electrochemical Society, Vol. 152, pp. C769-C775 (2005).
[24]P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans, and H. Deligianni, "Damascene copper electroplating for chip interconnections," IBM Journal of Research and Development, Vol. 42, pp. 567-574 (1998).
[25]P. M. Vereecken, R. A. Binstead, H. Deligianni, and P. C. Andricacos, "The chemistry of additives in damascene copper plating," IBM Journal of Research and Development, Vol. 49, pp. 3-18 (2005).
[26]T. P. Moffat, D. Wheeler, and D. Josell, "Electrodeposition of copper in the SPS-PEG-Cl additive system I. Kinetic measurements: Influence of SPS," Journal of The Electrochemical Society, Vol. 151, pp. C262-C271 (2004).
[27]M. Tan and J. N. Harb, "Additive behavior during copper electrodeposition in solutions containing Cl−, PEG, and SPS," Journal of The Electrochemical Society, Vol. 150, pp. C420-C425 (2003).
[28]Z. V. Feng, X. Li, and A. A. Gewirth, "Inhibition due to the interaction of polyethylene glycol, chloride, and copper in plating baths: a surface-enhanced Raman study," The Journal of Physical Chemistry B, Vol. 107, pp. 9415-9423 (2003).
[29]W. P. Dow, H. S. Huang, M. Y. Yen, and H. C. Huang, "Influence of convection-dependent adsorption of additives on microvia filling by copper electroplating," Journal of The Electrochemical Society, Vol. 152, pp. C425-C434 (2005).
[30]K. Kondo, N. Yamakawa, Z. Tanaka, and K. Hayashi, "Copper damascene electrodeposition and additives," Journal of Electroanalytical Chemistry, Vol. 559, pp. 137-142 (2003).
[31]J. Kelly, T. Nogami, O. van der Straten, J. Demarest, J. Li, C. Penny, T. Vo, C. Parks, P. DeHaven, C. K. Hu and E. Liniger "Electrolyte additive chemistry and feature size-dependent impurity incorporation for Cu interconnects," Journal of The Electrochemical Society, Vol. 159, pp. D563-D569 (2012).
[32]W. Zhang, S. H. Brongersma, T. Conard, W. Wu, M. Van Hove, W. Vandervorst, and K. Maex, "Impurity incorporation during copper electrodeposition in the curvature-enhanced accelerator coverage regime," Electrochemical and Solid-State Letters, Vol. 8, pp. C95-C97 (2005).
[33]C. K. Hu, M. Angyal, B. C. Baker, G. Bonilla, C. Cabral, D. F. Canaperi, S. Choi, L. Clevenger, D. Edelstein, L. Gignac, E. Huang, J. Kelly, B. Y. Kim, V. Kyei-Fordjour, S. L. Manikonda, J. Maniscalco, S. Mittal, T. Nogami, C. Parks, R. Rosenberg, A. Simon, Y. Xu, T. A. Vo and C. Witt "Effect of impurity on Cu electromigration," AIP Conference Proceedings, pp. 57-67 (2010).
[34]M. Stangl, M. Lipták, J. Acker, V. Hoffmann, S. Baunack, and K. Wetzig, "Influence of incorporated non-metallic impurities on electromigration in copper damascene interconnect lines," Thin Solid Films, Vol. 517, pp. 2687-2690 (2009).
[35]S. Muranaka, M. Sueyoshi, K. Mori, K. Maekawa, M. Fujisawa, and K. Asai, "Effect of impurities and microstructure of Cu electroplated film on reliability of Cu interconnects using CuAl alloy seed," Microelectronic Engineering, Vol. 105, pp. 91-94 (2013).
[36]K. N. Chen, A. Fan, C. S. Tan, and R. Reif, "Bonding parameters of blanket copper wafer bonding," Journal of Electronic Materials, Vol. 35, pp. 230-234 (2006).
[37]C. Yu, Y. Yang, H. Lu, and J. M. Chen, "Effects of Current Stressing on Formation and Evolution of Kirkendall Voids at Sn–3.5Ag/Cu Interface," Journal of Electronic Materials, Vol. 39, pp. 1309-1314 (2010).
[38]J. Yu and J. Y. Kim, "Effects of residual S on Kirkendall void formation at Cu/Sn–3.5 Ag solder joints," Acta Materialia, Vol. 56, pp. 5514-5523 (2008).
[39]C. Yu, J. Chen, Z. Cheng, Y. Huang, J. Chen, J. Xu, and H. Lu, "Fine grained Cu film promoting Kirkendall voiding at Cu3Sn/Cu interface," Journal of Alloys and Compounds, Vol. 660, pp. 80-84 (2016).
[40]H. Li, R. An, C. Wang, Y. Tian, and Z. Jiang, "Effect of Cu grain size on the voiding propensity at the interface of SnAgCu/Cu solder joints," Materials Letters, Vol. 144, pp. 97-99 (2015).
[41]J. Y. Wu, H. Lee, C. H. Wu, C. F. Lin, W. P. Dow, and C. M. Chen, "Effects of Electroplating Additives on the Interfacial Reactions between Sn and Cu Electroplated Layers," Journal of The Electrochemical Society, Vol. 161, pp. D522-D527 (2014).
[42]T. Y. Yu, H. Lee, H. L. Hsu, W. P. Dow, H. K. Cheng, K. C. Liu, and C. M. Chen, "Effects of Cu Electroplating Formulas on the Interfacial Microstructures of Sn/Cu Joints," Journal of The Electrochemical Society, Vol. 163, pp. D734-D741 (2016).
[43]H. Lee, T. Y. Yu, H. K. Cheng, K. C. Liu, P. F. Chan, W. P. Dow, and C. M. Chen, "Impurity Incorporation in the Cu Electrodeposit and Its Effects on the Microstructural Evolution of the Sn/Cu Solder Joints," Journal of The Electrochemical Society, Vol. 164, pp. D457-D462 (2017).
[44]Y. Liu, J. Wang, L. Yin, P. Kondos, C. Parks, P. Borgesen, D. W. Henderson, E. J. Cotts, and N. Dimitrov, "Influence of plating parameters and solution chemistry on the voiding propensity at electroplated copper–solder interface," Journal of Applied Electrochemistry, Vol. 38, pp. 1695-1705 (2008).
[45]Y. Liu, J. Wang, L. Yin, P. Kondos, C. Parks, P. Borgesen, D. W. Henderson, S. Bliznakov, E. J. Cotts, and N. Dimitrov, "Improving copper electrodeposition in the microelectronics industry," Electronic Components and Technology Conference, 2008. ECTC 2008. 58th, pp. 2105-2110 (2008).
[46]C. Yu, Y. Yang, J. Chen, J. Xu, J. Chen, and H. Lu, "Effect of deposit thickness during electroplating on Kirkendall voiding at Sn/Cu joints," Materials Letters, Vol. 128, pp. 9-11 (2014).
[47]C. K. Lin, C. Chen, D. T. Chu, and K. N. Tu, "Communication—Formation of Porous Cu3Sn by High-Temperature Current Stressing," ECS Journal of Solid State Science and Technology, Vol. 5, pp. P461-P463 (2016).
[48]L. D. Chen, M. L. Huang, and S. M. Zhou, "Effect of electromigration on intermetallic compound formation in line-type Cu/Sn/Cu interconnect," Journal of Alloys and Compounds, Vol. 504, pp. 535-541 (2010).
[49]K. Yamanaka, Y. Tsukada, and K. Suganuma, "Electromigration effect on solder bump in Cu/Sn–3Ag–0.5 Cu/Cu system," Scripta Materialia, Vol. 55, pp. 867-870 (2006).
[50]S. H. Lee and C. M. Chen, "Electromigration in a Sn-3 wt.% Ag-0.5 wt.% Cu-3 wt.% Bi Solder Stripe Between Two Cu Electrodes Under Current Stressing," Journal of Electronic Materials, Vol. 40, pp. 1943-1949 (2011).
[51]Y. Jung and J. Yu, "Electromigration induced Kirkendall void growth in Sn-3.5 Ag/Cu solder joints," Journal of Applied Physics, Vol. 115, pp. 083708 (2014).
[52]T. Takenaka, S. Kano, M. Kajihara, N. Kurokawa, and K. Sakamoto, "Growth behavior of compound layers in Sn/Cu/Sn diffusion couples during annealing at 433–473K," Materials Science and Engineering: A, Vol. 396, pp. 115-123 (2005).
[53]A. Paul, C. Ghosh, and W. J. Boettinger, "Diffusion parameters and growth mechanism of phases in the Cu-Sn system," Metallurgical and Materials Transactions A, Vol. 42, pp. 952-963 (2011).
[54]S. Kumar, C. A. Handwerker, and M. A. Dayananda, "Intrinsic and interdiffusion in Cu-Sn system," Journal of Phase Equilibria and Diffusion, Vol. 32, pp. 309-319 (2011).
[55]L. Zhang, X. y. Fan, C. w. He, and Y. h. Guo, "Intermetallic compound layer growth between SnAgCu solder and Cu substrate in electronic packaging," Journal of Materials Science: Materials in Electronics, Vol. 24, pp. 3249-3254 (2013).
[56]J. W. Yoon and S. B. Jung, "Effect of isothermal aging on intermetallic compound layer growth at the interface between Sn-3.5 Ag-0.75 Cu solder and Cu substrate," Journal of Materials Science, Vol. 39, pp. 4211-4217 (2004).
[57]K. Zeng and K. N. Tu, "Six cases of reliability study of Pb-free solder joints in electronic packaging technology," Materials Science and Engineering: R: reports, Vol. 38, pp. 55-105 (2002).
[58]X. Hu, T. Xu, L. M. Keer, Y. Li, and X. Jiang, "Microstructure evolution and shear fracture behavior of aged Sn3Ag0.5Cu/Cu solder joints," Materials Science and Engineering: A, Vol. 673, pp. 167-177 (2016).
[59]C. Yang, F. Le, and S. W. Ricky Lee, "Experimental investigation of the failure mechanism of Cu–Sn intermetallic compounds in SAC solder joints," Microelectronics Reliability, Vol. 62, pp. 130-140 (2016).
[60]M. H. Lu and K. C. Hsieh, "Sn-Cu intermetallic grain morphology related to Sn layer thickness," Journal of Electronic Materials, Vol. 36, pp. 1448-1454 (2007).
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊