臺灣博碩士論文加值系統

本論文主要研究在三維鰭式電晶體中S/D應力源對電晶體的應力響應。研究方法主要使用ANSYS應力分析模擬器，畫出鰭式電晶體結構，並在有限元素分析(FEM)架構下模擬鰭式電晶體元件之三維通道應力分佈，以及比較P型與N型鰭式電晶體不同尺寸材料對應力大小與分佈的影響。在使用SolidWorks建構電晶體結構時，不易更改尺寸參數，因此直接以ANSYS軟體構圖。最後再利用Sentaurus TCAD與二階壓阻模型及二階壓阻模型修正計算出遷移率對應力之變化，並探討兩個壓阻模型之間的差異性以及準確性。

The stress response of stressor to transistor in three-dimensional fin field-effect transistor is mainly researched in this paper. The research method is to draw the structure of fin field-effect transistor mainly by Ansys stress analysis emulator, emulate the stress distribution of three-dimensional channels of fin field-effect transistor modules under the finite element analysis (FEM) framework, and compare the effect of P-type and N-type field-effect transistors of different sizes and materials on stress intensity and distribution. ANSYS is directly used for drawing because it’s not easy to change the dimension parameters when SolidWorks is used to construct the structure of transistor. Finally, Sentaurus TCAD, second-order piezoresistance model and adjustment of second-order piezoresistance model are used to calculate the change of counter stress of mobility, and the difference and accuracy between the two piezoresistance models are discussed.

誌謝詞 i
中文摘要 ii
Abstract iii
目錄 iv
圖目錄 v
表目錄 vii
第一章 導論 1
1–1 研究動機 1
1–2 文獻回顧 2
1-2-1 鰭式場效電晶體 2
1-2-2 應變矽簡介 4
1-2-3 壓阻模型的沿革 9
第二章 模擬軟體介紹 14
2–1 ANSYS軟體簡介 14
2-1-1 有限元素法 15
2–2 Sentaurus TCAD之Sband功能與模型簡介 19
2-2-1 區域與材料(Regions and Materials) 19
2-2-2 電極(Contact) 20
2-2-3 非局部線(Nonlocal Lines) 20
2-2-4 元件座標軸(Device Coordinate Axes) 20
第三章 應變工程的理論基礎與應力模擬 22
3–1 應力與應變 22
3–2 晶格不匹配所產生應力 30
第四章 鰭式電晶體之應力模擬與分析 34
4–1 建立鰭式電晶體之模型 34
4–2 參雜濃度及尺寸對應力的影響 39
第五章 鰭式電晶體之遷移率模型與壓阻模型 47
5–1 遷移率增益之計算 47
5–2 二階壓阻模型及二階壓阻模型修正之差異 52
第六章 總結與未來展望 63
6–1 總結 63
6–2 未來展望 65
參考文獻 66

[1] T. Ghani et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” IEEE Int’l Electron Devices Meeting Technical Digest, pp. 11.6.1–11.6.3, Dec. (2003).
[2] 半導體產業推動辦公室專刊No.27，pp.22，2007。
[3] S. Thompson, P. Packan, and M. Bohr, “MOS Scaling: Transistor Challenges for the 21st Century,” Intel Technology Journal, Q3 (1998).
[4] Xuejue Huang, Wen-Chin Lee, Charles Kuo et. al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol 48, no. 5, pp. 880–886 (2001).
[5] D. Hisamoto, T. Kaga, E. takeda, “Impact of the vertical SOI 'Delta' Structure on Planar Device Technology,” IEEE Transactions on Electron Devices, vol 38, issue 6 (1991).
[6] 台灣電子材料與元件協會，「新世代積體電路製程技術」，臺灣東華書局股份有限公司，pp.258-289，2011.
[7] K. Rim et al., “Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs,” IEDM Tech. Dig., 517 (1995).
[8] 魏拯華、李敏鴻、劉致為，「奈米電子學」，臺大出版中心，2006。
[9] Charles S. Smith, “Piezoresistance Effect in Germanium and Silicon”, Physical Review, vol 94, no. 1 (1954).
[10] Jeff Wu, Xin Wang, “Stress Engineering for 32nm CMOS Technology Node”, IEEE, pp113-116 (2008).

[11] D. Colman, R. T. Bate, and J. P. Mize, “Mobility Anisotropy and Piezoresistance in Silicon p-Type Inversion Layers”, Journal of Applied Physics, vol 39, no. 4, (1968).
[12] 羅儀庭，「矽鍺合金電子遷移率之研究」，碩士論文，2014。
[13] 蔡政原，「具源/汲極應力元的金氧半場效電晶體元件之應力響應研究」，碩士論文，2014
[14] Fabian M. Bufler, Axel Erlebach, and Mohamed Oulmane, “Hole Mobility Model With Silicon Inversion Layer Symmetry and Stress-Dependent Piezoconductance Coefficients”, IEEE electron device letters, vol. 30, no. 9 ( 2009).
[15] 劉晉奇，電腦輔助工程分析入門：ANSYS速學，五南圖書出版股份有限公司，2009。
[16] T. Benabbas, P. Francois, Y. Androussi, and A. Lefebvre, ”Stress relaxation in highly strained InAs/GaAs structures as studied by finite element analysis and transmission electron microscopy”, AIP, pp2763-2767, (1996).
[17] 宋裕祺、蘇進國、張荻薇，「有限元素法在鋼斜張橋結構分析之應用」“Applications of Finite Element Method on Structural Analysis of Steel Cable-Stayed Bridges”，中日「鋼結構工程」研討會，Tainan，Taiwan，2007。
[18] 賴育良、林啟豪、謝忠祐，「ANSYS電腦輔助工程分析」，儒林圖書有限公司，台北，pp. 1-5~1-7，2002。
[19] G. Abstreiter, H. Brugger, T. Wolf, H. Jorke, and H. J. Herzog, “Strain-induced two-dimensional electron gas in selectively doped Si/SixGe1-x superlattices”, Phys. Rev. Lett. 54, 2441 (1985).

[20] Synopsys Sentaurus Manual 201206.
[21] Suyog Gupta, Victor Moroz, Lee Smith, Qiang Lu, and Krishna C. Saraswat, “7-nm FinFET CMOS Design Enabled by Stress Engineering Using Si, Ge, and Sn ”, IEEE Transactions on Electron Devices, vol 61, no. 5 (2014).
[22] Darsen D.Lu, Angada B. Sachid, Yao-Min Huang, Yi-Ju Chen, Chun-Chi Chen, Min-Cheng Chen, Chenming Hu, “Stressor Design for FinFETs with Air-Gap Spacers”, 2017 International Symposium on VLSI Technology, System and Application (2017).