臺灣博碩士論文加值系統

本論文探討應用於物件偵測雷達系統子電路研發，子電路種類包含V頻段相移器、由低雜訊放大器及混頻器所構成的直接降頻W頻段接收端以及一應用市售調變器晶片與威爾京生功率分波器之專題。本論文自行設計的晶片都是使用TSMC 90nm CMOS製程。論文內容包含元件及電路設計、模擬分析、晶片量測、結果討論。論文整體主軸可分為六個章節：
第一章簡述研究背景，並說明選擇V頻段與W頻段的理由。
第二章對雷達系統子電路作介紹，包含相移器、低雜訊放大器、混頻器的基本概念、以及此三種電路常見的基本架構與各項效能參數。
第三章為應用於V頻段的向量組合式相移器的研究。在此章使用藍基耦合器與平衡轉不平衡轉換器產生I+、I–、Q+、Q–共4個相差90度相位的訊號進入向量組合器進行向量組合，此方式透過電壓控制可以達到360度全相位。晶片總面積為0.732×0.948 mm2，在1.2V的供應電壓之下量測總功耗為27.6 mW。饋入損失依輸出相位不同介於–11.88 dB到–6.63 dB間，P1dB為0 dBm，輸出相位在62.5 GHz到66 GHz誤差在5度內。
第四章為應用於W頻段的直接降頻接收機設計。由一4級的共源極低雜訊放大器及一雙平衡主動混頻器構成。低雜訊放大器使用電晶體並聯及源極退化技巧，後模擬增益為15.59 dB、雜訊指數為6.66dB。混頻器為直接降頻式混頻器，將78 GHz射頻訊號降至基頻，並使用了電流注入技巧。後模擬轉換增益為13.2 dB、雜訊指數為14 dB。接收端整體晶片面積為1.12×0.735 mm2，接收端整體後模擬轉換增益為25.27 dB，雜訊指數為8.17 dB，P1dB為–24dBm，供應電壓1.2V之下功耗為57 mW。
第五章使用一市售調變器晶片及自行佈局的威爾京生功率放大器在印刷電路板上實作一調變電路。在調變器的基頻輸入調頻連續波訊號並將其升頻至12 GHz後由威爾京生功率分波器將訊號分成兩路。
第六章總結各章的研究成果並探討未來的研究方向。

This thesis presents the study of subcircuits for the object-detection radar systems, including a V-band phase shifter, an application of a vendor provided modulator chip with an on-board Wilkinson power divider, and a W-band direct down-conversion receiver which consists of a low noise amplifier (LNA) and a mixer. All of the designed chips in this thesis are implemented in the TSMC 90nm CMOS process. The content of this thesis includes the design of passive devices and circuits, simuation and measurement results, conlusion and discussion. There are 6 chapters in this thesis:
Chapter 1 presents the motivation of the study and the benefits of systems implemented in V-band and W-band.
Chapter 2 presents the introduction of the subcircuits for radar system, including the phase shifter, the low noise amplifier and the mixer. Furthermore, this chapter presents general considerations in the designs of subcircuits of a radar system, including performance parameters for RF circuits.
Chapter 3 shows the design of a V-band vector combination phase shifter. The phase shifter consists of a Lange coupler, 3 balance-to-unbalance converters (Baluns) and a vector combiner. Four signals with 90 degree phase difference, i.e. I+, I–, Q+, and Q– generated by a Lange coupler and two Baluns are input to the vector combiner. Vector combination technique is able to control the output phase by voltage. Continuous phase shift of 360 degree have been measured. The chip area is 0.732×0.948 mm2, and the power comsumption is 27.6 mW under a 1.2V supply. The range of S11 under different control voltage is from –11.88 dB to –6.63 dB. The measured P1dB is 0 dBm. The frequency range for the phase error less than 5 degree is from 62.5 GHz to 66 GHz.
Chapter 4 shows the designs of a W-band direct down-conversion receiver, which cosists of a 4-stage common-source low nois amplifier and a double blanced mixer. Parallel-connected transistors and the source degeneration technique are adopted in the proposed LNA. The simulation results of S21 is 15.69 dB while the simulated noise figure is 6.66 dB. The current bleeding technique is adopted in the direct down-conversion mixer. The simulation result of the power conversion gain is 13.2 dB and the simulated noise figure is 14 dB. The whole chip size of the receiver is 1.12×0.735 mm2. The simulated power conversion gain of the receiver chain is 25.27 dB and the noise figure is 8.17 dB at 78 GHz. The 1-dB compression point is –24 dBm. The power comsumption of the proposed W-band receiver is 57 mW under a 1.2V supply.
Chapter 5 presents an application of a vendor provided modulator chip and a self-designed Wilkinson divider on a PCB board. The baseband FMCW signal is up-converted to the 12 GHz band by the modulator and its power is divided by the Wilkinson divider for the transmitter and the receiver, respectively.
Chapter 6 conludes the thesis and bring a short discussion.

第一章　緒論 1
1.1 無線射頻系統 1
1.2 毫米波及其應用 3
1.3 論文架構 4
第二章　射頻接收機電路介紹 5
2.1 低雜訊放大器介紹 5
2.2 混頻器介紹 7
2.2.1 混頻器原理 7
2.2.2 混頻器架構介紹 7
2.2.2.1 單平衡式主動混頻器 8
2.2.2.2 雙平衡式主動混頻器 10
2.3 相移器 15
2.4 重要特性參數介紹 16
2.4.1 雜訊指數 16
2.4.2 線性度 18
2.4.2.1 1dB增益壓縮點 18
2.4.2.2 三階截距點 20
2.4.3 轉換增益 22
2.4.4 穩定度 23
2.4.5 隔離度 23
第三章　應用於V-Band向量組合相移器 25
3.1 前言 25
3.2 電路架構 27
3.3 電路設計 27
3.3.1 藍基耦合器介紹及其規格 27
3.3.2 65GHz藍基耦合器設計架構與模擬結果圖 28
3.3.3平衡轉不平衡轉換器介紹及其規格 30
3.3.3.1 Marchand Balun及其規格 31
3.3.4 65GHz Marchand Balun設計架構與模擬結果圖 32
3.3.5 向量組合器 34
3.3.6 電路佈局 36
3.4 模擬結果 38
3.5 量測結果 41
3.6 電路結果與討論 48
第四章　應用於W-Band之接收端 50
4.1 前言 50
4.2 電路架構 50
4.3 電路設計 51
4.3.1 低雜訊放大器電路設計 51
4.3.1.1 傳輸線 52
4.3.1.2 電晶體並聯 52
4.3.1.3 源極退化 53
4.3.2 混頻器設計電路設計 54
4.3.2.1 交叉耦合PMOS電流注入技巧 54
4.3.2.2 應用於W-Band混頻器 58
4.3.3 接收端電路佈局 60
4.4 電路模擬結果 61
4.4.1 低雜訊放大器模擬結果 61
4.4.2 混頻器模擬結果 65
4.4.3 接收端模擬結果 72
4.4.4 電路結果與討論 76
第五章　應用於12GHz調變器與威爾京生分波器 77
5.1 計畫介紹 77
5.2 應用於12GHz調變器與威爾京生分波器 79
5.2.1 電路簡介與元件選擇 79
5.2.2 威爾京生功率分波器 81
5.3 PCB板佈局 83
5.4 量測結果 87
5.5 結果與討論 91
第六章　結論與未來展望 92
參考文獻 94

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