|
[1] D. M. Pozar , Microwave and RF design of wireless systems, New York: John Wiley, 2001 [2]高曜煌,射頻鎖相迴路IC設計,滄海書局,2005年。 [3] IEEE Standard Letter Designations for Radar-Frequency Bands, IEEE Standard 521-2002, 2003. [4] M. Marcus, B. Pattan, "Millimeter wave propagation; spectrum management implications", IEEE Microwave Magazine, vol. 6, no. 2, pp. 54-62, June 2005. [5] 劉深淵、楊清淵,”鎖相迴路,” 滄海書局,2006 [6] B.Razavi, Design of Analog CMOS Integrated Circuits, 1st Edition McGraw-Hill, 2001. [7] B.Razavi, RF Microelectronics, Second Ed., Pearson Education International, Dec.2011. [8] Mark Van Paemel, “Analysis of a Charge-Pump PLL: a new model,” IEEE Trans. Communications, Vol. 42,no. 7, pp. 2490-2498, July 1994. [9] F. M. Gardner, ”Charge-Pump Phase-Lock Loops,” IEEE Trans. Communications, vol. 28, no. 5, pp. 691-700, May 1997. [10] S. Kim, "A 960-Mb/s/pin interface for skew-tolerant bus using low-jitter PLL", IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997. [11] J. Rogers, C. Plett, F. Dai, Integrated circuit design for high-speed frequency synthesis, ARTECH HOUSE, INC. , 2006 [12] Ningbing Hou, Zhiqun Li, "Design of high performance CMOS charge pump for phase-locked loops synthesizer", Proceedings of the 15th Asia-Pacific conference on Communications, pp. 197-200, 2009. [13] Behzad Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE Journal of Solid-state Circuits, vol. 31, n. 3, pp. 331-343, March 1996. [14] D. B. Leeson, “A Simple Model of Feedback Oscillator Noise Spectrum,” in Proc. of IEEE, pp. 329-330, February 1966. [15] T.H. Lee, A. Hajimiri, "Oscillator phase noise: a tutorial", Solid-State Circuits IEEE Journal of, vol. 35, no. 3, pp. 326-336, 2000. [16] J.J. Rael, A.A. Abidi, “Physical processes of phase noise in differential LC oscillators,” in IEEE Custom Integrated Circuits Conference, pp. 569-572, 2000. [17] E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE Journal of Solid-Stare Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001. [18] B. Razavi, “RF Microelectronics second edition,” Pearson Education International, Dec. 2011. [19] L. Romano, S. Levantino, A. Bonfanti, C. Samori, and A. L. Lacaita,“Phase noise and accuracy in quadrature oscillators,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 1, pp. 161–164. , 2004. [20] H. Chang, X. Cao, U.K. Mishra and R.A. York, “Phase Noise in Coupled Oscillators: Theory and Experiment,” IEEE Trans. on Microwave Theory and Techniques, vol.45, no.5, pp 604-615, May 1997. [21]J. Yuan, C. Svensson, “High speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol.24, pp 62-70, Feb. 1989. [22] Anantha Chandrakasan; William J. Bowhill; Frank Fox “Design of High-Performance Microprocessor Circuits,” NEW York:IEEE Press,2001,p.240 [23]H.H.Chang, Design and Application of CMOS Digital/Analog Delay-Locked Loops",Ph.D. Dissertation,NTU,2004. [24] L. Dai, R. Harjani, "CMOS switched-op-amp-based sample-and-hold circuit", IEEE Journal of Solid-State Circuits, vol. 35, pp. 109-113, 2000. [25]P. Andreani, “A 2GHz, 17% tuning range quadrature CMOS VCO with high figure-of-merit and 0.6° phase error”, Proceedings of the 28th European Solid-State Circuits Conference, 2002. pp. 815-818, Sept. 2002. [26] Y. Mo, E. Skafidas, R. Evans, I. Mareels, "A 40 Ghz power efficient static CML frequency divider in 0.13-µm CMOS technology for high speed millimeter-wave wireless systems", IEEE ICCSC , pp. 812-815, May 2008. [27] A. Axholt, H. Sjöland, "A 2.25 mw inductor-less 24 ghz cml frequency divider in 90nm cmos", Circuit Theory and Design (ECCTD) 2011 20th European Conference on. IEEE, pp. 77-80, 2011. [28]Chien-Nan Kuo, Huan-Sheng Chen, Tzu-Chao Yan, "A K-Band CMOS Quadrature Frequency Tripler Using Sub-Harmonic Mixer", IEEE Microwave and Wireless Component Letter, vol. 19, no. 12, pp. 822-824, Dec 2009. [29]B. R. Jackson, F. Mazzilli, and C. E. Saavedra, “A frequency tripler using a subharmonic mixer and fundamental cancellation,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp. 1083–1090, May 2009. [30]Z. Zhang, Z. Chen, L. Tsui, and J. Lau, “A 930 MHz CMOS DC-offset free direct-conversion 4-FSK receiver,” in IEEE Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2001, pp. 290–291. [31]J. F. Osorio, el. al., "A 21. 7-to-27. 8GHz 2. 6-Degrees-rms 40mW Frequency Synthesizer in 45nm CMOS for mm-Wave Communication Applications", IEEE ISSCC 2011. [32]O. Richard, A. Siligaris, F. Badets, C. Dehos, C. Dufis, P. Busson, P. Vincent, D. Belot, P. Urard, "A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications", ISSCC Dig. Tech. Papers, pp. 252-253, Feb. 2010.
|