臺灣博碩士論文加值系統

本論文是研究半導體積體電路製程中，接觸窗孔的金屬沉積製程前之離子蝕刻的電漿電源與偏壓電源的匹配，以降低因為直流偏壓造成的電荷累積，這些累積電荷容易造成漏電流的產生，該漏電流在電性測試中無法被攔檢，只能在良率檢測當中被攔檢，進而造成晶圓良率的損失。
除了電荷累積之外，因為離子蝕刻轟擊原生氧化物，使得原生氧化物掉落至接觸窗孔的底部形成再沉積現象，後續鈦及氮化鈦沉積的階梯覆蓋效應變差，致使沉積金屬鎢導線(W)時，發生鎢穿刺現象，該現象在電性測試或是良率測試當中被攔檢。
為了改善漏電流及鎢穿刺現象所造成的損失，因此利用電漿電源與偏壓電源之匹配及減少離子蝕刻量，來達到降低累積電荷及鎢穿刺的狀況，以達到提升晶圓良率的目的。
實驗數據顯示，調整電漿電源與偏壓電源的匹配及降低離子蝕刻量，皆能達到減少漏電進而提升良率，尤其是在金屬與元件電極間接觸窗孔的改善效果特別明顯，金屬層間接觸窗孔也有獲得些微的改善。

This thesis is focused on the matching of plasma power and bias power in the ion etching process for the contact and via holes prior to depositing the metal film in the semiconductor IC process. Due to the ion etching process, the accumulated charges would cause the generation of leakage current, which would further result in the yield loss of wafer.
In addition to the charge accumulation issue, the native oxide is bombarded by ion etching, and then the bombarded native oxide would fall into the bottom of the contact or via holes, resulting in a re-deposition phenomenon. Owing to this unwanted issue, the step coverage of the subsequent titanium and titanium nitride deposition would become worse, resulting in the phenomenon of tungsten puncture in the metallization process of tungsten, which would be detected by the following electrical test or yield test.
In order to improve the yield loss caused by the leakage current and tungsten puncture phenomenon, the matching between plasma power and bias power and the reduction of ion etching amount are adopted to minimize the cumulative charge and tungsten puncture.
Experimental data shows that the adjustment of plasma power and bias power matching and the reduction of ion etching amount can achieve the purpose of reducing the leakage current to improve the yield, especially in the contact holes between the device’s electrodes and the interconnection line. However, the via holes between the interconnection lines only show little improvement.

總目錄
誌謝辭．．．．．．．．．．．．．．．．．．．．．．．． i
摘要．．．．．．．．．．．．．．．．．．．．．．．．． ii
Abstrac．．．．．．．．．．．．．．．．．．．．．．．．iii
總目錄．．．．．．．．．．．．．．．．．．．．．．．． v
表目錄．．．．．．． ．．．．．．．．．．．．．．．．．vii
圖目錄．．．．．．． ．．．．．．．．．．．．．．．．．viii
第一章 緒論．．．．．．．．．．．．．．．．．．．．． 1
1.1 前言．．．．．．．．．．．．．．．．．．．．． 1
1.2 研究動機與目的．．．．．．．．．．．．．．．． 4
第二章 接觸窗孔的製程介紹．．．．．．．．．．．．．． 5
2.1　接觸窗孔的形成．．．．．．．．．．．．． ．． 5
2.2 接觸窗孔阻障層的製程介紹．．．．．．．． ．． 9
2.3 離子蝕刻的機制及參數介紹．．．．．．．． ．． 13
2.3.1 離子蝕刻的沿革．．．．．．．．． ．．． 15
2.3.2 離子蝕刻的參數介紹．．．．．．．． ．． 16
2.3.3 製程參數對離子蝕刻的影響．．．．． ．． 17
2.3.4 蝕刻時間對均勻性的影響．．．． ．．．． 18
2.3.5 脫氧溫度對離子蝕刻的影響．．．．． ．． 20
2.3.6 電漿電源對直流偏壓的影響．． ．．．．． 22
2.3.7 電漿與偏壓電源的匹配效應． ．．．．．． 23
2.3.8　直流偏壓的介紹及效應．．． ．．．．．． 26
第三章　接觸窗孔離子蝕刻的實驗參數規劃．．．．．．．． 27
3.1 金屬與元件電極間的接觸窗孔． ．．．．．．．． 27
3.2 金屬層間的接觸窗孔．．．．．．．．．． ．．． 32
第四章 實驗結果與討論．．．．．．．．．．．．．．．． 34
4.1 金屬與元件電極間接觸窗孔．．．．．． ．．．． 34
4.1.1 直流偏壓反應值分析．．．．．． ．．．． 34
4.1.2　電性與良率測試分析．．．．．． ．．．． 37
4.2 金屬層間接觸窗孔．．．．． ．．．．．．．．． 46
4.2.1　直流偏壓反應值分析．．．．．． ．．．． 46
4.2.2 電性與良率測試分析．．．．． ．．．．． 49
第五章 結論及未來展望．．．．．．．．．．．．．．．． 52
參考文獻．．．．．．．．．．．．．．．．．．．．．．． 53

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