本研究探討無接面(Junctionless)環繞式閘極具多通道結構對溫度及運用摻雜濃度關聯性。簡化通道式側壁邊襯蝕刻圖案化技術(Simplified sidewall spacer patterning technique)來定義奈米線通道(Nanowire)，藉由多通道方式以及再結合環繞式元件間的電特性差異閘極結構可呈現出更穩定及優異的電性。首先,針對環繞式無接面及反轉模式(Inversion mode)元件多晶矽奈米線通道在較大溫度範圍 (從液態氮氣七十七絕對溫度到四百一十絕對溫度) 研究對溫度關聯性探討，無接面元件的次臨界擺幅以及臨界電壓具有對溫度相同趨勢,但溫度高於室溫時,有明顯的轉折點.這是因為無接面元件的通道具有重摻雜, 在高溫時,通道雜質散射效應較反轉式元件來的明顯。此外，還討論了在各種溫度下具有不同摻雜濃度的無接面元件的行為。然而，當摻雜濃度達到1 × 1020cm-3時，表面電位顯示出較高的對溫度的抗擾性，並且通道中的電位能障變(barrier potential)得非常小。

其次，奈米線通道和閘極結構均由雙側壁邊襯蝕刻圖案化技術過程定義。 閘極長度可以通過氧化物硬式掩模 (Oxide hard mask) 濕式蝕刻浸漬時間進行微調，獲得約二十奈米、三十奈米和五十奈米的閘極長度元件。 此外，無接面元件的電氣特性均顯示溫度依賴性，當溫度高達高於室溫時，高溫下的雜質散射和光子散射而使得電流開狀態電流顯示溫度獨立性。

本篇論文最後，在上述三組元件包含 (一) 環繞式無接面及反轉模式元件具有一微米和點二十五微米元件閘極長度、(二) 環繞式無接面元件具有一微米和點二十五微米閘極長度在不同摻雜濃度1 × 1019cm-3、5 × 1019cm-3、1 × 1020cm-3元件、(三) 環繞式無接面元件具有二十奈米、三十奈米和五十奈米閘極長度。這些具有多個通道的多晶矽無接面元件特性也已被證明。在施加多重奈米線通道結構後，對於具有無接面元件具有一微米和點二十五微米元件閘極長度，這些器件顯示出元件與元件間特性變化變穩定以及較高的電流開關比（> 109）。而對於具有各種摻雜濃度的無接面元件具有一微米和點二十五微米元件閘極長度。摻雜濃度為1×1020 cm -3的無接面元件的臨界電壓變化比1×1019 cm -3無接面元件差，當隨著奈米線通道結構數目增加到二十奈米線, 此時電流開關比而升高到2.5×108。雖然通過多通道結構可以獲得閘極長度為二十奈米、三十奈米和五十奈米無接面元件的較小變化，二十奈米閘極長度無接面元件仍然遭受嚴重的短通道效應 (Short channel effect) ，經由穿透式電子顯微鏡(TEM)影像結構分析我們發現，由於在閘極定義的過蝕刻而造成的底切現象，此現象將造成多通道元件容易有嚴重的短通道效應, 而造成比五十奈米無接面元件更差的電特性。然而，具有五十奈米無接面元顯示出更好的閘極控制能力，而不會受到嚴重的短通道效應和溫度敏感性，表現出低功率器件和未來晶片進行三維空間垂直整合(3D IC)應用的潛力。

In this study, the temperature dependence and doping concentration of junctionless gate-all-around (GAA) devices with multiple channels were studied. The multiple poly-Si nanowire channels of ~12 nm nanowire width were prepared by a simplified sidewall spacer patterning process, and employed the GAA structure, with the device obtaining excellent electrical characteristics. First, the temperature-dependent characteristics of the GAA JL and inversion mode (IM) devices with a wide temperature range (77 to 410 K) were characterized. The JL devices showed nearly the same tendencies in subthreshold swing (S.S.) and threshold voltage (Vth) with respect to the change in temperature. There were obvious kinks at temperatures up to 300 K, due to the JL device’s heavily doped channel and the fact that the impurity scattering effect in the channel is more significant than in its IM counterpart at high temperatures. Moreover, the behavior of JL devices with different doping concentrations at various temperatures was also discussed. However, the surface potential exhibited higher immunity to temperature and the barrier potential in the channel became very small when the doping concentration reached 1 × 1020 cm-3.
Second, both NW and gate structures were defined by the double sidewall spacer patterning process. The gate length can be fine-tuned by oxide hard mask wet dipping time, with gate lengths of ~20 nm, 30 nm, and 50 nm gate obtained. Furthermore, all electrical characteristics in the JL device showed temperature dependence, with the exception of the ON status current’s temperature independence up to 300K due to the combination of impurity scattering and photon scattering at high temperature.
Finally, these poly-Si JL devices with multiple channels were also demonstrated. JL devices with dimensions of 1-m and 0.25-m with the multiple NW channel structures of 1 × 1019 cm-3 devices show small variations and a high ON/ OFF current ratio (> 109). For 1-m and 0.25-m JL devices with various doping concentrations, the variations of Vth in devices with a doping concentration of 1 × 1020 cm-3 were worse than that of 1 × 1019 cm-3 devices, while the ON/ OFF current ratio increased with the NWs increasing to 20 NWs could be achieved to ~2.5 × 108. Although a smaller variation can be obtained in JL devices with gate lengths of 20nm, 30nm, and 50 nm through the multiple channel structure, the 20 nm device still suffers from serious SCEs and shows poorer electrical characteristics than the 50 nm device due to the undercut of the gate structure. However, the JL device with 50-nm gate length shows better gate controllability without suffering serious SCEs and temperature sensitivity, and thereby exhibits good potential for being a low-power device with future 3D IC applications.

摘要 i
Abstract iii
Acknowledgement v
Contents vi
Figure Captions x
Table Captions xv

Chapter 1 1
Introduction 1
1.1 Current Trend of CMOS Technology and Future Roadmap 1
1.2 Overview of Multiple Gate Structure 2
1.3 Overview of poly-Si Thin-Film-Transistor 4
1.4 Overview of Silicon Nanowire Fabrication 5
1.5 Overview of Junctionless Transistor Device 7
1.6 Temperature Effect on Junctionless Transistor Device 9
1.6.1 Variation of Variation of Subthreshold Swing with Temperature 12
1.6.2 Variation of Threshold Voltage with Temperature
13
1.7 Doping Concentration Effect on Junctionless Transistor Device 14
1.8 Motivation 16
1.9 Thesis Organization 17
References 20

Chapter 2 28
Temperature- and doping-concentration-dependent Characteristics of Junctionless Gate-all-Around poly-Si Thin-Film-Transistors 28
2.1 Introduction 28
2.2 Junctionless and Inversion Mode Transistor 29
2.3 Experimental 32
2.3.1 Fabrication Steps of GAA poly-Si NW Thin-Film Transistor 32
2.3.2 Structure Analyses for Gate-All-Around poly-Si Junctionless Thin-Film-Transistor 34
2.3.3 Definition and Extraction of Electrical Parameters 35
2.4 Results and Discussion 37
2.4.1 Electric Characteristics of GAA JL and IM poly-Si NW Transistor Device 37
2.4.2 Temperature-dependent Characteristics of GAA JL and IM poly-Si NW Transistor Device 39
2.4.3 Doping-concentration-dependent Characteristics of GAA JL poly-Si NW Transistor Device at Various Temperatures
48
2.5 Summary 55
References 56

Chapter 3 59
Temperature Dependence of Gate-All-Around poly-Si Nanowire Junctionless Transistors with 20/30/50 nm Twin Gate
60
3.1 Introduction 60
3.2 Experiments 61
3.2.1 Fabrication Steps of GAA poly-Si NW Thin-Film Transistor with Double Spacer Patterning Technique
61
3.2.2 Structure Analyses for Gate-All-Around poly-Si Thin-Film-Transistor… 65
3.3 Results and Discussion 66
3.3.1 Characteristics of GAA JL poly-Si NW Transistor Device with Gate Length 20/30/50 nm 66
3.3.2 Temperature Dependence of GAA JL poly-Si NW Transistor Device with Gate Length 20/30/50 nm at Various Temperature Region. 68
3.3.3 Output Characteristic of GAA JL poly-Si NW Transistor Device with Gate Length 20/30/50 nm 73
3.3.4 Activation Energy of GAA JL poly-Si NW Device with Gate Length 20/30/50 nm 75
3.4 Summary 76
References 77

Chapter 4 82
Gate-All-Around poly-Si Nanowire Junctionless Thin-Film-Transistors with Multiple Channels 82
4.1 Introduction 82
4.2 Experiment 83
4.2.1 Simplified Double Spacer Patterning Technique
83
4.2.2 Fabrication of Gate-All-Around Junctionless poly-Si NW Transistor Devices 85
4.2.3 Structure Analyses for Gate-All-Around poly-Si Thin-Film-Transistor .86
4.3 Results and Discussion 89
4.3.1 Electrical Characteristics with Multiple Channels of Gate-All-Around poly-Si Junctionless with Gate Length 0.25-μm and 1-μm 89
4.3.2 Electrical Characteristics with Multiple Channels of Gate-All-Around poly-Si Junctionless LG= 0.25 μm with Various Doping Concentration. 98
4.3.3 Electrical Characteristics with Multiple Channels of Gate-All-Around poly-Si Junctionless with Gate Length 20/30/50 nm. 103
4.4 Summary 112
References 114

Chapter 5 118
5.1 Conclusion 118
5.2 Further Prospects 120
Vita 121
Publication List 122

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