本篇論文主要分為兩個主題，第一部分為並並回授低雜訊放大器的分析，第二部分為利用低損耗電感設計LC梯次輸入匹配低雜訊放大器。
第一部分主要討論電阻或電容並並回授的輸入匹配網路，接著利用雜訊轉換矩陣與雜訊參數來推導電容並並回授共源極電晶體的最低雜訊因子，並且透過模擬來驗證結果，最後，我們實作三顆並並回授寬頻低雜訊放大器，並且與其他不同輸入匹配架構的寬頻低雜訊放大器作比較。
第二部分介紹積體被動元件GIPD製程以及打線電感的原理與特點，接著透過模擬電感來觀察品質因子的改善，此外，針對不同操作頻段的LC梯次輸入匹配網路做模擬並討論雜訊指數的變化，最後，我們實作了兩顆使用GIPD整合0.18µm CMOS製程的低雜訊放大器以及一顆使用打線電感的低雜訊放大器，並與未使用低損耗電感的晶片作比較。

This thesis consists of two parts, the first part is the analysis of shunt-shunt feedback LNAs, and the second part is the design of LC-ladder input match LNAs utilizing low-loss inductors.
In the first part, resistor and capacitor shunt-shunt feedback input match networks are discussed. Then, noise parameters of a common source FET device with a capacitor shunt-shunt feedback is derived utilizing noise transformation matrix. Furthermore, the results are verified by simulations. Finally, three shunt-shunt feedback LNAs are designed to compare with other LNAs with different input match networks.
In the second part, the principle and characteristics of GIPD technology and bondwire inductors are introduced. The improvement of quality factor of inductors is observed from simulations. In addition, LC-ladder input match networks with different values of components are simulated to discuss the effect to the noise figure. Finally, two LNAs using GIPD 0.18µm CMOS process and one LNA using bondwire inductors are designed to compare with LNAs using standard CMOS process.

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 v
圖目錄 vii
表目錄 x
第一章 導論 1
1-1 研究動機及相關研究近況發展 2
1-2 論文組織架構 3
第二章 並並回授低雜訊放大器 4
2-1 並並回授低雜訊放大器架構分析 5
2-1-1 電阻並並回授輸入匹配 5
2-1-2 輸入RLC之電阻並並回授輸入匹配 7
2-1-3 電容並並回授輸入匹配 9
2-1-4 雙級並並回授寬頻低雜訊放大器增益 12
2-2 共源極電容並並回授雜訊分析 14
2-3 並並回授寬頻低雜訊放大器實作 25
2-3-1 實作一：利用電阻串電容並並回授製作3.3~8.2GHz寬頻
低雜訊放大器(WIN 0.15µm pHEMT) 25
2-3-2 實作二：利用電阻串電容並並回授製作4~8GHz寬頻低雜
訊放大器(TSMC 0.18µm CMOS) 34
2-3-3 實作三：4~8GHz雙級並並回授寬頻低雜訊放大器
(TSMC 0.18µm CMOS) 42
2-3-4 實驗結果與文獻比較 49
第三章 利用低損耗電感製作LC梯次輸入匹配低雜訊放大器 51
3-1 前言 52
3-2 積體被動元件製程簡介 52
3-3 三階式LC梯次輸入匹配操作頻段與雜訊模擬分析 55
3-4 利用GIPD製程整合CMOS電路實作 63
3-4-1 實作一：2.1~8.8GHz三階式LC梯次寬頻低雜訊放大器
(GIPD整合TSMC 0.18µm CMOS製程) 63
3-4-2 實作二：2.4/5GHz雙頻低雜訊放大器
(GIPD整合TSMC 0.18µm CMOS製程) 73
3-5 打線電感簡介 82
3-6 利用打線電感實作低雜訊放大器 84
3-6-1 實作三：比較有無打線電感之2.4/5GHz雙頻低雜訊放大器
(TSMC 0.18µm SiGe BiCMOS) 84
第四章 結論 92
參考文獻 95

第二章：
[1] H.-K. Chen, Y.-S. Lin, and S.-S. Lu, “Analysis and design of a 1.6-28-GHz compact wideband LNA in 90-nm CMOS using a π-match input network,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 8, pp. 2092–2104, Aug. 2010.
[2] Y.-C. Hsiao, C. C. Meng, and C. Yang, ”Design optimization of single-/dual-band FET LNAs using noise transformation matrix,” IEEE Trans. Microw. Theory Techn., vol. 64, no. 2, pp. 519-532, Feb. 2016.
[3] Y.-T. Lin, H.-C. Chen, Y.-S. Lin and S.-S. Lu,”3-10-GHz ultra-wideband low-noise amplifier utilizing miller effect and inductive shunt-shunt feedback technique,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 9, pp. 1832–1843, Sep. 2007.
[4] M. Weststrate. And S. Sinha, “Noise Optimization of a Wideband Capacitive Shunt-Shunt Feedback LNA Design Suitable for Software-defined Radio,” IEEE International Conference on Electronics, Circuits and Systems, pp. 619-622, Dec. 2009.
[5] 李孟哲, “寬頻pHEMT低雜訊放大器之最佳化設計與2.4GHz雙模態功率放大器,” 國立交通大學碩士論文, Jul. 2016.
[6] Andrea Bevilacqua, and Ali M. Niknejad, “An Ultrawideband CMOS Low-Noise Amplifier for 3.1–10.6-GHz Wireless Receivers,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2259-2268, Nov. 2004.
[7] S. Shekhar; X. Li; D. J. Allstot, “A CMOS 3.1-10.6GHz UWB Employing Stagger-Compensated Series Peaking,” IEEE RFIC Symposium, pp. 4, Jun. 2006.
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第三章：
[1] 倪榮鴻, “雙頻帶和寬頻源級退化電感低雜訊放大器雜訊的最佳化設計,” 國
立交通大學碩士論文, Oct. 2015.
[2] 張凱鈞, “用積體被動製程技術的CMOS低雜訊放大器與CMOS單刀雙擲開
關設計,” 國立交通大學碩士論文, Jul. 2016.
[3] A. Bevilacqua and A. M. Niknejad, “An ultrawideband CMOS lownoiseamplifier for 3.1–10.6 GHz wireless receivers,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2259–2268, Dec. 2004.
[4] S. Shekhar, X. Li, and D. J. Allstot, “A CMOS 3.1-10.6 GHz UWB LNA employing stagger-compensated series peaking,” IEEE RadioFreq. Integrated Circuits Symp., Jun. 2006, pp. 49–52.
[5] Y.-C. Hsiao, C. C. Meng, and M.-C. Li, “Analysis and Design of Broadband LC-Ladder FET LNAs Using Noise Match Network,”
[6] L.-H. Lu et al., “A compact 2.4/5.2-GHz CMOS dual-band low-noise amplifier,” IEEE Microwave and Wireless Components Letters, vol. 15,no.10, pp. 685-687, Oct. 2005.
[7] 張智凱, “2.4/5.8-GHz 低功率低雜訊CMOS直接降頻接收機,” 國立交通大學碩士論文, July 2010.
[8] G. Moschetti, N. Wadefalk, P.-Å. Nilsson, M. Abbasi, L. Desplanque, X.Wallart and J. Grahn, “Cryogenic InAs/AlSb HEMT Wideband Low-Noise IF Amplifier for Ultra-Low Power Applications,” IEEE Microw. Wireless Comp. Lett., vol. 22, no. 3, pp. 144-146, Mar. 2012.
[9] G. Vendelin, A. Pavio, U. Rohde, Microwave Circuit Design Using Linear and Nonlinear Techniques, 2nd, John Wiley & Sons, 2005.