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研究生:劉宇軒
研究生(外文):Liu, Yu-Hsuan
論文名稱:具動態時脈控制技巧之高性能電流-電壓雙模式直流-直流降壓穩壓器
論文名稱(外文):A Novel High-Performance Current-Voltage Dual-Mode DC-DC Buck Converter with Adaptive Clock Control Technique
指導教授:洪崇智
指導教授(外文):Hung, Chung-Chih
口試委員:陳柏宏李育民
口試委員(外文):Chen, Po-HungLee, Yu-Min
口試日期:2017-07-26
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:中文
論文頁數:93
中文關鍵詞:動態時脈控制高性能電流模式電壓模式直流-直流降壓穩壓器
外文關鍵詞:Adaptive clock controlHigh performanceCurrent-modeVoltage-modeDC-DCBuck converter
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本論文提出一具有高轉換效率、快速暫態響應以及低成本之電流-電壓雙模式直流-直流降壓穩壓器。本次提出之電流-電壓雙模式可以根據電路不同的環境需求,將其控制模式切換至電流模式或是電壓模式,以求最好的整體效能。而透過本次提出的動態時脈控制技巧,可以使電路在做暫態響應時能夠改變其切換頻率,進而改善其輸出變化,也同時加速其反應時間。此外,在緩啟動電路上亦提出一全新控制電路,以解決緩啟動電路中的嵌入式電容因為漏電流的誤判造成電路瞬間啟動時產生出的大電流。在本次設計中,除了輸出電感、輸出電容以及分壓電阻外,其餘電路皆實現在晶片中,故在面積及花費上也有所改善。此電流-電壓雙模式控制降壓型穩壓器的電路設計是由台灣積體電路製造股份有限公司2P4M 0.35μm互補式金氧半製程來實現。輸入電壓為2.7~4.2V,輸出電壓為0.9~2.7V,此規格適用於手持式產品之應用。當輸出負載瞬間從50mA抽載至500mA時,其回復時間與輸出電壓變化分別小於5μs與94mV,與傳統架構相比,則分別減少了83%的回復時間及36%的電壓變化。本次設計之電路在負載電流為100mA時可以達到其最大轉換效能95.784%。在輸出負載電流為30mA~600mA的範圍內,其轉換效能皆可達90%以上。透過本次提出之設計,可以使直流-直流降壓穩壓器之整體性能有效地提升。
This thesis presents a novel high-efficiency, fast-transient, and low-cost current-voltage dual-mode (CVDM) dc-dc buck converter using adaptive clock controller (ACC). The proposed CVDM control can switch the control method between current mode and voltage mode to improve the performance according to different situations. By using the ACC technique, the circuit can dynamically and smoothly adjust the switching frequency during the transient response to improve the undershoot, overshoot voltage, and recovery time. Moreover, the proposed on-chip soft-start circuit can eliminate the excess large current during the startup of the regulator. In this work, only an output inductor, capacitor, and feedback resistors are outside the system on chip (SoC), so the chip area and the cost can be reduced effectively. The circuit was implemented by TSMC 0.35-μm CMOS process. The input voltage is 2.7~4.2V and the output voltage is 0.9~2.7V accordingly, which is suitable for portable devices. The transient recovery time and undershoot voltage are less than 5μs and 94mV, respectively, for the load current change from 50mA to 500mA. As compared with the traditional structure without any fast transient technique, the performance of transient recovery time and undershoot voltage can be reduced by 83% and 36%, respectively. The maximum conversion efficiency is 95.784% at 100mA load current. Above 90% conversion efficiency can be achieved for load current from 30mA to 600mA. With the proposed techniques, the performance of the dc-dc converter is improved significantly.
摘要 i
ABSTRACT ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 3
第二章 直流-直流穩壓器概論 4
2.1 穩壓器分類 4
2.1.1 線性穩壓器簡介(Linear Regulator) 4
2.1.2 切換式穩壓器簡介(Switching Regulator) 6
2.1.3 切換式電容穩壓器簡介(Switching Capacitance Regulator) 7
2.1.4 穩壓器分類比較 8
2.2 切換式穩壓器分類 9
2.2.1 降壓切換式穩壓器(Buck Converter) 9
2.2.2 升壓切換式穩壓器(Boost Converter) 11
2.2.3 升降壓切換式穩壓器(Buck-Boost Converter) 13
2.3 切換式穩壓器控制電路分類 16
2.3.1 脈波寬度調變(Pulse Width Modulation, PWM) 16
2.3.2 脈波頻率調變(Pulse Frequency Modulation, PFM) 17
2.4 切換式穩壓器規格定義與說明 20
2.4.1 轉換效率(Efficiency) 20
2.4.2 線性調節度(Line Regulation) 22
2.4.3 負載調節度(Load Regulation) 22
2.4.4 輸出電壓漣波(Output Voltage Ripple) 23
2.4.5 暫態響應(Transient Response) 23
第三章 降壓型切換式穩壓器架構 26
3.1 切換式穩壓器控制模式 26
3.1.1 電壓模式控制(Voltage-Mode Control) 26
3.1.2 電流模式控制(Current-Mode Control) 27
3.2 電流模式控制基本理論 29
3.2.1 次諧波震盪(Sub-Harmonic Oscillation) 29
3.2.2 斜率補償(Slope Compensation) 31
3.3 系統頻率響應分析 32
3.3.1 電壓模式模型分析 32
3.3.2 電流模式模型分析 37
第四章 高性能電流-電壓雙模式降壓穩壓器 42
4.1 系統設計概念 42
4.2 降壓型切換式穩壓器電路設計 43
4.2.1 脈衝省略緩啟動電路(Pulse-Skipping Soft-Start Circuit) 44
4.2.2 動態時脈控制器(Adaptive Clock Controller) 48
4.2.3 補償電路與校正機制(Compensator and Calibration) 51
4.2.4 高精準度電流偵測電路(High Accuracy Current Sensing Circuit) 56
4.2.5 快速暫態控制電路(Fast Transient Control Circuit) 58
4.2.6 斜率補償器(Slope Compensator) 60
4.2.7 誤差放大器(Error Amplifier) 62
4.2.8 遲滯型比較器(Hysteresis Comparator) 63
4.2.9 停滯時間控制器與驅動電路(Dead-Time Controller and Drivers) 64
4.3 降壓型切換式穩壓器模擬結果 65
4.3.1 脈衝省略緩啟動電路(Pulse-Skipping Soft-Start Circuit) 66
4.3.2 動態時脈控制器(Adaptive Clock Controller) 67
4.3.3 快速暫態控制電路(Fast Transient Control Circuit) 69
4.3.4 電流模式暫態模擬 70
4.3.5 電壓模式暫態模擬 72
4.3.6 電流-電壓雙模式暫態模擬 74
4.3.7 線性調節度(Line Regulation) 75
4.3.8 負載調節度(Load Regulation) 76
4.3.9 轉換效率(Efficiency) 77
第五章 降壓型切換式穩壓器佈局與量測 79
5.1 電路佈局考量 79
5.2 晶片量測考量 81
5.2.1 外部環境考量 81
5.2.2 暫態響應考量 82
5.2.3 線性調節度考量 82
5.2.4 負載調節度考量 82
5.2.5 轉換效率考量 82
5.2.6 模式切換考量 82
5.3 晶片量測結果 83
5.3.1 暫態響應量測結果 84
5.3.2 線性調節度量測結果 86
5.3.3 負載調節度量測結果 87
5.3.4 轉換效率量測結果 88
5.3.5 參考文獻比較結果 89
第六章 結論與未來展望 91
6.1 結論 91
6.2 未來展望 91
參考文獻 92
[1] H. H. Ko, “A high efficiency synchronous CMOS switching buck regulator with accurate current sensing technique,” MS Thesis, Department of Electrical Engineering, National Central University, 2007.
[2] G. A. Rincon-Mora and P. E. Allen, “A low-voltage, low quiescent current, Low drop-out regulator,” IEEE J. Solid-State Circuits, vol. 33, no. 1, pp.36-44, Jan.1998.
[3] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics. Norwell, MA: Kluwer, 2001.
[4] C. I. Chiu, “On the Implementation of an Ultra-Wide-Load High-Efficient DC-DC Buck Converter,” MS Thesis, Department of Electrical Engineering, National Central University, 2011.
[5] P. Y. Wu, S. Y. S. Tsui, and P. K. T. Mok, “Area- and Power- Efficient Monolithic Buck Converters With Pseudo-Type III Compensation,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1446–1455, Aug. 2010.
[6] J. J. Chen, W. T. Hsu, J. H. Yu, Y. S. Hwang, and C. C. Yu, “A fast-transient-response buck converter with split-type III compensation and charge-pump circuit technique,” International Power Electronics Conference (IPEC), pp. 2910-2913, May 2014.
[7] D. Mattingly, “Designing stable compensation networks for single phase voltage mode buck regulators,” Intersil Technical Brief, Dec. 2003.
[8] S.-W. Lee, “Demystifying Type II and Type III Compensators Using Op- Amp and OTA for DC/DC Converters,” Texas Instruments Application Report, Jul. 2014.
[9] Y. D. Lee, “Compensation Design for Peak Current-Mode Buck Converters,” Richtek Application Note, Apr. 2014.
[10] P. J. Liu, C. Y. Hsu, and Y. H. Chang, “Techniques of dual-path error amplifier and capacitor multiplier for on-chip compensation and soft-start function,” IEEE Trans. Power Electron., vol. 30, no. 3, pp. 1403-1410, 2015.
[11] P. J. Liu, Y. C. Hsu, and Y. H. Chang, “A current-mode buck converter with a pulse-skipping soft-start circuit,” IEEE International Conference on Power Electronics and Drive Systems, pp. 262-265, 2013.
[12] H. W. Huang, C. Y. Hsieh, K. H. Chen, and S. Y. Kuo, “Adaptive frequency control technique for enhancing transient performance of DC-DC converters,” Proc. 33rd Eur. Solid-State Circuits Conf. (ESSCIRC), pp. 174-177, Sep. 2007.
[13] C. C. Wong, H. H. Wu, M. H. Shih, and C. L. Wei, “Design of a Fast Transient Current-Mode Buck DC-DC Converter,” International Future Energy Electronics Conference (IFEEC), pp.767-771, 2013.
[14] Y. H. Lam, W. H. Ki, and D. Ma, “Loop gain analysis and development of high-speed high-accuracy current sensors for switching converters,” Proc. 2004 IEEE Int. Symp. Circuits and Systems, vol. 5, pp. 828–831, May 2004.
[15] T. Man, P. Mok, and M. Chan, “Design of Fast-Response On-Chip Current Sensor for Current-Mode Controlled Buck Converters with MHz Switching Frequency,” IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 389–392, 2007.
[16] H. W. Huang, H. H. Ho, C. C. Chien, K. H. Chen, G. K. Ma, and S. Y. Kuo, “Fast transient DC-DC converter with on-chip compensated error amplifier,” Proc. ESSCIRC, pp. 324–327, 2006.
[17] C. Y. Hsieh and K. H. Chen, “Adaptive pole-zero position (APZP) technique of regulated power supply for improving SNR,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2949–2963, Nov. 2008.
[18] Y. H. Lee, S. C. Huang, S. W. Wang, and K. H. Chen, “Fast transient (FT) technique with adaptive phase margin (APM) for current mode DC–DC buck converters,” IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 10, pp. 1781-1793, Oct. 2012.
[19] P. Y. Wang, L. T. Wu, and T. H. Kuo, “A Current-Mode Buck Converter with Bandwidth Reconfigurable for Enhanced Efficiency and Improved Load Transient Response,” Proc. Tech Papers A-SSCC, pp. 69-72, Nov. 2014.
[20] F. F. Ma, W. Z. Chen, and J. C. Wu, “A monolithic current-mode buck converter with advanced control and protection circuit,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1836–1846, Sep. 2007.
[21] C. F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 3–14, Jan. 2004.
[22] Y. H. Lee, S. J. Wang, and K. H. Chen, “Quadratic differential and integration technique in V2 control buck converter with small ESR capacitor,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 829–838, Apr. 2010.
[23] P. J. Liu, W. S. Ye, J. N. Tai, H. S. Chen, J. H. Chen, and Y. J. E. Chen, “A high-efficiency CMOS dc-dc converter with 9-μs transient recovery time,” IEEE Trans. Circuits and Syst. I, Reg. Papers, vol. 59, no. 3, pp. 575–583, Mar. 2012.
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