[1] http://www.cadence.com/eu/Documents/MicrosoftPowerPoint ToT2013openend.pdf
[2] https://verificationacademy.com/verification-horizons/october-2012-volume-8-issue-3/improving-analog-mixed-signal-verification-productivity
[3] A. Demir and J. Roychowdhury, “A Reliable and Efficient Procedure for Oscillator PPV Computation with Phase Noise Macromodeling Applications,” IEEE Trans. on Computer-Aided Design, pp. 188-197, Feb. 2003.
[4] G. Richard, “Analog/Mixed-Signal Behavioral Modeling – When to Use What”, Cadence Design Communities, February 2011.
[5] C.-C. Kuo, Y.-C. Wang, and C.-N. J. Liu, “An Efficient Bottom-Up Extraction Approach to Build Accurate PLL Behavioral Models for SOC Designs,” in Proc. Great Lakes Symp. on VLSI, pp. 286-290, Apr. 2005.
[6] A. Mounir, A. Mostafa, and M. Fikry, “Automatic Behavioural Model Calibration for Efficient PLL System Verification,” in Proc. Design, Automation and Test in Europe Conf., pp. 280-285, 2003.
[7] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, A. Baschirotto, “Behavioral modeling of switched-capacitor sigma-delta modulators,” IEEE Trans. on Circuits and Systems I, pp. 352-364, Mar 2003.
[8] W.-H. Cheng, C.-C. Kuo, P.-J. Chen, Y.-M. Wang, and C.-N. J. Liu, “An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor Sigma-Delta Modulator,” in Proc. Int’l Workshop on Behavioral Modeling and Simulation, pp. 17-21, Sep. 2007.
[9] M. Rewienski, J. White, “A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices,” IEEE Trans. on Computer-Aided Design, pp. 155-170, Feb. 2003.
[10] R.A Rutenbar; G.G.E. Gielen; J Roychowdhury, “Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs”, Proceedings of the IEEE, pages 640-669, march 2007.
[11] P. Wambacq, F. Fernández, G. Gielen, W. Sansen, and A. Rodríguez-Vázquez, “Efficient symbolic computation of approximated small-signal characteristics” IEEE Journal. Solid-State Circuits, vol. 30, pages. 327–330, Mar 1995.
[12] C.-J.Richer. ; Shi., “Canonical symbolic analysis of large analog circuits with determinant decision diagrams”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages. 1-18, January 2000
[13] L. T. Pillage and R. A. Rohrer, “Asymptotic waveform evaluation for timing analysis”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, pages. 352–366, April 1990.
[14] J.-R. Li and J. White, “Efficient model reduction of interconnect via approximate system gramians”, IEEE Transacitons on Computer-Aided Design of Integrated Circuit and Systems , pages. 380–383, November 1999.
[15] K. Gallivan, “Asymptotic waveform evaluation via a Lanczos method”, Pergamon, pages 75-80, April 1944
[16] F. Mourad, T-C. Esteban, C-L. Rafael. et.al, “Analog/RF and Mixed-Signal Circuit Systematic Design”, Rafael, 2013, ISBN 978-3-642-36329-0
[17] M. Rewienski and J. White, “A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices”, IEEE Transacitons on Computer-Aided Design of Integrated Circuit and Systems, Nov 2001.
[18] http://www.analog.com/static/imported-files/tech_docs/dsp_book_Ch15.pdf
[19] 陳建宇, “基於迴歸分析之類比電路行為模型自動產生器”, 中央大學碩士論文, July 2015[20] M. Eick, “Structure and signal path analysis for analog and digital circuits,”Ph.D. Dissertation, Dept. Electr. Eng. Inf. Technol., Technische Universitt München, München, Germany, 2013
[21] 樓禹慷,“自動辨識混合訊號電路中數位區塊之方法”,中央大學碩士論文,July 2016[22] 王綉文, “適用於混合訊號設計的自動化電路區塊降為模型產生器”, 中央大學碩士論文, July 2014[23] T. Massier, “The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis”, IEEE Computer-Aid Design of Integrated Circuit and Systems, December 2008
[24] C.Wenger, “Method of Modeling Analog Circuits in Verilog for Mixed-signal Design Simulations,” IEEE ECCTD 2013 European Conference on
[25] Yu-Ching Liao et.al, “LASER: layout-aware analog synthesis environment on laker”, Great lakes symposium on VLSI (GLSVLSI), May 2013.