臺灣博碩士論文加值系統

動態隨機存取記憶體在許多電子系統中為一個關鍵元件，為維持其資料完整性，動態隨機存取記憶體必須執行週期性的復新動作，然而復新動作本身卻是一個非常耗能的動作。另一方面，動態隨機存取記憶體會受到軟性錯誤的影響而將會使其成為一個不可靠的元件。因此，動態隨機存取記憶體需要有效的節能及可靠度提升技術。
錯誤更正碼及硬體冗餘方法兩者皆為廣泛使用於提升可靠度及良率的技術。
在本論文中，一個混合式錯誤更正碼及硬體冗餘技術(Hybrid ECC and redundancy technique, HEAR)被提出用於降低動態隨機存取記憶體的復新功耗及提升其可靠度。在本文的第一部分，所提出的HEAR 技術被用於降低動態隨機存取記憶體待機時的復新功耗，該技術使用BCH 碼及錯誤位元修正模組來延展復新週期使得動態隨機存取記憶體的復新功耗得以被降低。透過結合BCH 碼及錯誤位元修正模組，所提出的混合式錯誤更正碼及硬體冗餘元件技術可以最小化錯誤更正碼所帶來的負面影響。分析結果表示所提出的技術可以節省2Gb DDR3 DRAM 40~70%的待機能量。檢查碼及錯誤更正碼電路的面積消耗只需為只使用錯誤更正碼策略時的63%及53%。
在本論文的第二部分中，HEAR 技術被用於動態隨機存取記憶體快取的可靠度提升。該技術可以更正動態隨機存取記憶體中的硬性錯誤及軟性錯誤。評估結果表示當使用可更正兩位元的錯誤更正碼及一位元的錯誤位元修正模組時其提供的可供的可靠度略低於兩位元錯誤更正碼及三位元錯誤更正碼，然而其效能花費僅為兩位元及三位元錯誤更正碼的0.125%。另一方面，三倍模組冗餘方法被用於更正快取的標籤即使這會將標籤複製成三份。整體的儲存空間花費被限制於12.5%，可靠度及效能花費都比單一位元錯誤更正碼效果更佳。

Dynamic random access memory (DRAM) is one key component in many electronic systems. To preserve the data integrity, DRAM needs to execute the refresh operation periodically. However, refresh operation is a power-hungry operation. On the other hand, DRAM is prone to soft errors such that it is an unreliable component in a system. Therefore, effective power-reduction and reliability-enhancement techniques are needed for DRAMs.
Error correction code (ECC) and hardware redundancy are widely used techniques for enhancing
the reliability and yield of DRAMs. In this thesis, we proposed a hybrid ECC and hardware
redundancy (HEAR) technique for reducing refresh power and enhancing reliability of DRAMs.

In the first part of this thesis, the proposed HEAR technique is used to reduce the refresh power
of DRAMs in standby mode. The HEAR technique uses a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to prolong the refresh period such that the refresh power of DRAM can be reduced. By combining BCH and EBR, the HEAR technique can minimize
the adverse effects caused by the ECC technique. Analysis results show that the proposed HEAR scheme can achieve 40∼70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63% and 53% of that of the ECC-only, respectively.

In the second part of the thesis, a reliability-enhancement technique based on HEAR technique for DRAM caches is proposed. The reliability-enhancement technique can correct the hard errors and the soft errors in the DRAM cache. The evaluation result shows that when the configuration of the reliability-enhancement technique uses double error correction ECC and single bit repair, the provided reliability of the data part is close but slightly lower than that of double error correction or
triple error correction. However, the performance overhead can be only 0.125% of that of double error correction or triple error correction ECC at most. On the other hand, TMR is used to correct the tag part of the cacheline even though the tag is triplicated. The overall storage overhead for the DRAM cache is limited at 12.5%. Both reliability and performance overhead are more outstanding than single error correction ECC.

1 Introduction 1
1.1 Dynamic Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Organization of DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Errors in DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.3 Power Consumption of DRAM . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.4 DRAM Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.1 Low-Power Techniques for DRAM . . . . . . . . . . . . . . . . . . . . . 6
1.2.2 Reliability Enhancement Techniques for DRAM Caches . . . . . . . . . . 7
1.3 Thesis Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 Proposed Hybrid ECC and Redundancy (HEAR) Technique . . . . . . . . 7
1.3.2 Reducing Standby Power of DRAMs Using The Proposed HEAR Technique 8
1.3.3 Reliability-Enhancement Scheme for DRAM Caches Using The Proposed
HEAR Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Proposed Fault-Tolerant Technique for DRAMs 10
2.1 Hardware Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.1 Triple-Module Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 Error-Bit Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Information Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Time Redundancy and Software Redundancy . . . . . . . . . . . . . . . . . . . . 17
2.4 Proposed Hybrid ECC and Redundancy (HEAR) Technique . . . . . . . . . . . . 17
3 Reducing Standby Power of DRAMs Using HEAR Technique 21
3.1 Proposed HEAR technique for Reducing Standby Power of DRAMs . . . . . . . . 22
3.1.1 Why Hybrid ECC and Redundancy Scheme Is Used? . . . . . . . . . . . . 22
3.1.2 Concept of HEAR Technique for Reducing Standby Power of DRAMs . . 24
3.2 Simulation Result and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4 Reliability-Enhancement Scheme for DRAM Caches Using HEAR Technique 38
4.1 Proposed Hybrid Protection Scheme for DRAM Caches . . . . . . . . . . . . . . . 38
4.1.1 Protection of Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.2 Protection of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.3 Proposed Hybrid Protection Scheme . . . . . . . . . . . . . . . . . . . . . 39
4.2 Modeling of The Proposed Hybrid Protection Scheme . . . . . . . . . . . . . . . . 45
4.2.1 Reliability Model of The Header . . . . . . . . . . . . . . . . . . . . . . . 46
4.2.2 Reliability Model of The Data . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3 Architecture of The Proposed Hybrid Protection Scheme . . . . . . . . . . . . . . 48
4.4 Simulation Result and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.4.1 Single-Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.4.2 Reliability Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4.3 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5 Conclusions and Future Work 64
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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