臺灣博碩士論文加值系統

隨著製程進步，目前的超大型積體電路設計愈來愈複雜，單晶片系統( System on Chip , SOC ) 成為設計的選項之一，由於一個系統通常同時包含數位電路與類比電路，因此類比/混合訊號(Analog/mixed-signal, AMS)電路的驗證在開發晶片的流程中變的重要許多。在這篇論文中，我們採用波動數位濾波器(Wave Digital Filter, WDF)的原理，將類比電路轉成對應的數位電路來進行仿真。此方法使用入射波與反射波的方式描述電路特性，可以將每個類比元件對應至波動數位濾波器架構的數位元件，達成與數位電路一起模擬的目標。
本研究根據WDF架構仿真流程之相關文獻，開發硬體實現流程，建立仿真電路硬體架構，並實現於FPGA板上，使得整個仿真流程完整。也添加了定點數設計概念到硬體實現流程中來降低複雜度，並發展了定點數轉換流程。關於非線性的MOS元件，也成功以查表法的方式實作出來，解決了MOS元件數位化的問題。由實驗結果得知，定點數設計與浮點數設計的硬體資源使用率相當，準確度與HSPICE模擬波形相比，相關係數皆有在0.98以上，但於處理速度方面來說，定點數設計快浮點數約4倍多，因此相較於浮點數設計，定點數設計是個更加的選擇。

With the advance of process technologies, the design of Very-Large-Scale Integration (VLSI) circuits is becoming more complex. System on Chip (SOC) has become one possible option of VLSI design. Because SOC designs usually contain both analog and digital circuits, it is important to have an Analog/Mixed-Signal (AMS) verification flow for chip development. In this thesis, we adopt Wave Digital Filter theory to map analog circuits into digital circuits for emulating analog circuits. This method uses incident and reflected waves to model circuit characteristics. Each analog component can be transformed into digital component in WDF framework to support the co-simulation with digital circuits.
Based on the relevant research of WDF emulation process, this thesis develops the hardware implementation flow to establish the hardware structure of the emulator. The whole emulator has been implemented on FPGA to verify the whole flow of WDF emulation. In addition, this thesis adopts the fixed-point design concept to the hardware implementation to reduce the complexity and develops fixed-point conversion flow. About the non-linear MOS components, we also successfully implement the table lookup approach on FPGA to solve the digitalization issue. According to the experimental results, the hardware resource usage of the fixed-point design and the floating-point design is similar. In terms of accuracy, the correlation coefficient of waveform between WDF and HSPICE is higher than 0.98. However, the processing speed of fixed-point design is more than 4 times than that of floating-point design. Therefore, compared to floating-point design, fixed-point design is an appropriate choice.

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
1 第一章、緒論 1
1-1 研究動機 1
1-2 相關研究 3
1-2-1 場列式可程式類比陣列(FPAA) 3
1-2-2 可程式化類比元件陣列(PANDA) 5
1-3 論文結構 7
2 第二章、背景知識 8
2-1 數位濾波器(Digital Filter)模型 8
2-2 波動數位濾波器(Wave Digital Filter) 10
2-2-1 波動數位濾波器模型 10
2-2-2 配線器(Adaptor) 13
2-2-3 非線性半導體場效電晶體模型(MOSFET) 17
2-2-4 新式J型配線器(J-type adaptor) 22
3 第三章、定點數硬體設計方法 25
3-1 類比仿真器的仿真流程 25
3-2 硬體實現平台 27
3-3 線性電路 31
3-3-1 電路元件與配線器 31
3-3-2 定點數轉換 40
3-3-3 仿真電路硬體實現 41
3-4 非線性半導體場效電晶體實作 44
4 第四章、實驗結果 46
4-1 實驗環境 46
4-2 線性RC電路 46
4-3 T型橋式電路(Bridge-T) 50
4-4 P型金氧半場效電晶體(PMOS) 53
4-4-1 定點數設計與浮點數設計 53
4-4-2 新式非線性模型與線性小訊號模型 57
5 第五章、結論與未來工作項目 61
6 參考文獻 62

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