臺灣博碩士論文加值系統

現今的影像處理常會因為各種原因產生許多的雜訊，這些雜訊常會干擾到影像的利用，所以去除雜訊對於影像處理的應用是一種很重要的技術。在去除雜訊的技術之中，有一個很重要的問題是，如何在去除雜訊的同時，又不會破壞影像的特徵。而在去除雜訊的技術裡，雙邊濾波是一個在影像處理領域較常使用的一項去除雜訊的技術。雙邊濾波器的優點是在去除雜訊的同時還可以保留影像邊緣的細節，也因為這樣的特性，讓雙邊濾波器被應用在很多地方。
雙邊濾波器的運算複雜度很高，所以近年來有些研究提出雙邊濾波器的硬體實作來加快它的速度，雖然這些方法可以提高速度，但硬體電路的成本都還有改善的空間。在本論文中，我們提出一個可降低硬體成本且高速的雙邊濾波器。為了降低硬體成本，我們提出了一個LUT(look uptable)來減少所需要的記憶體空間。此硬體架構是以超大型積體電路設計(VLSI)的觀點來設計，使用Verilog硬體描述實作，並以Design Compiler來進行合成，最後用IC Compiler作後段APR。
實驗結果顯示，參考的文獻相比，我們的設計可以在不影響影像品質的前提下減少硬體成本且速度上也具有競爭力。

The image processing may have lots of image noising caused by various reasons, these noising may disturb the use of the image. Therefore, the image de-noising is a very important technology for the application of the image processing. The processing of image de-noising must not destroy the image features. The bilateral filter is one of the most popular image de-noising technology in the field of image processing. The advantage of bilateral filter is to retain the details of image edge when processing of image de-noising, which also make it widely used in the multitude of field.
The operations of Bilateral Filter is very complex, therefore some researches present the hardware-implement to improve the operating speed. Although these methods can improve the operating speed, the cost of hardware circuits still need to be reduced. In this paper, we present a method that reduces the cost for a high-speed Bilateral Filter. In order to reduce the cost of hardware, we present a LUT (Look up Table) to decrease the use of memory space. The basic hardware structure is designed by VLSI circuit, in accordance with the Verilog hardware-implement, and synthesized by the use of Design Compiler. Ultimately, finalising the back-end section of APR with IC Compiler.
In terms of research and relevant references, the empirical results reveal that our design can keep more competitive features in speed and reduced cost without lowering the image quality.

中文摘要 I
英文摘要 II
誌謝 III
目錄 IV
圖目錄 V
表目錄 VI
第一章 緒論 1
第一節 研究背景與動機 1
第二節 研究方法 3
第三節 論文架構 4
第二章 雙邊濾波器的演算法 5
第三章 研究方法 8
第一節 數據重組 9
第二節 光度權重和幾何權重架構 10
第三節 係數查表 11
第四節 核、基準架構 12
第五節 歸一化架構 13
第六節 管線化架構 14
第四章 實驗結果 16
第五章 結論 37
參考文獻 38

[1] C. Tomasi and P. Manduchi, “Bilateral filtering for gray and color images,” in Proc. IEEE ICCV, 1998, pp. 839–846.
[2] M.G. Mozerov and J. van de Weijer, “Accurate Stereo Matching by Two-Step Energy Minimization.” IEEE Trans. Image Process., vol. 24, no. 3, pp. 1153–1163, Mar. 2015.
[3] C. T. Huang, “Bayesian Inference for Neighborhood Filters With Application in Denoising,” IEEE Trans. Image Process., vol. 24, no. 11, pp. 4299–4311, Nov. 2015.
[4] N. H. Kaplan and I. Erer, “Bilateral Filtering-Based Enhanced Pansharpening of Multispectral Satellite Images,” IEEE Geosci. Remote Sens. Lett., vol. 11, no. 11, pp. 1941–1945, Nov. 2014.
[5] Q. Yang, J. Tang, and N. Ahuja, “Efficient and Robust Specular Highlight Removal,” IEEE Trans. Patt. Anal Mach. Intell., vol. 37, no. 6, pp. 1304–1311, Jun. 2015.
[6] Z. Li, J. Zheng; Z. Zhu; and S. Wu, “Selectively Detail-Enhanced Fusion of Differently Exposed Images With Moving Objects,” IEEE Trans. Image Process., vol. 23, no. 10, pp. 4372–4382, Oct. 2014.
[7] G. Petschnigg, R. Szeliski, M. Agrawala, M. Cohen, H. Hoppe, and K. Toyama, “Digital photography with flash and no-flash image,” ACM Trans. Graph., vol. 23, no. 3, pp. 664–672, Aug. 2004.
[8] S. S. Ieng, J. P. Tarel, and P. Charbonnier, “Modeling non-Gaussian noise for robust image analysis,” in Proc. Int. Conf. Comput. Vis. Theory Appl. (VISAPP), Barcelona, Spain, 2007, pp. 183–190.
[9] L. Caraffa, J. P. Tarel, and P. Charbonnier, “The guided bilateral filter：When the joint/cross bilateral filter becomes robust,” IEEE Trans. Image Process., vol. 24, no. 4, pp. 1199–1208, Apr. 2015.
[10] C. Charoensak and F. Sattar, “FPGA design of a real-time implementation of dynamic range compression for improving television picture,” in Proc. IEEE ICICS, 2007, pp. 1–5.
[11] H. Dutta, F. Hannig, J. Teich, B. Heigl, and H. Hornegger, “A design methodology for hardware acceleration of adaptive filter algorithms in image processing,” in Proc. IEEE ASAP, 2006, pp. 331–340.
[12] T. Q. Vinh, J. H. Park, Y.-C. Kim, and S. H. Hong, “FPGA implementation of real-time edge-preserving filter for video noise reduction,” in Proc. IEEE ICCEE, 2008, pp. 611–614.
[13] A. Gabiger-Rose, M. Kube, R. Weigel, and R. Rose, “An FPGA-based fully synchronized design of a bilateral filter for real-time image denoising,” IEEE Trans. Ind. Electron., vol. 6, no. 8, pp. 4093–4104, Aug. 2014.
[14] A. Benedetti, A. Prati, N. Scarabottolo,“Image convolution on FPGAs： the implementation of a multi-FPGA FIFO structure”, Proceedings of the 24th Euromicro Conference, Vasteras, Sweden, Vol.1, pp.123-130, 1998.