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研究生:林郁翔
論文名稱:應用於H.265之DCT/IDCT硬體架構設計
論文名稱(外文):Hardware architectures for the H.265-HEVC DCT/IDCT
指導教授:陳仁德陳仁德引用關係
口試委員:陳培殷蕭宇宏陳仁德
口試日期:2017-07-24
學位類別:碩士
校院名稱:國立彰化師範大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:中文
論文頁數:45
中文關鍵詞:硬體架構設計離散餘弦轉換管線化
外文關鍵詞:2D-DCT/IDCTH.265-HEVCPipeline
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數位多媒體改變了人類的溝通方式與生活方式,也改變了知識的傳播和傳播方式,對人類文明有著重大的影響,其中資料壓縮、視訊編碼是極為重要的。H.264-AVC(Advanced Video Coding)能提供高效率的視訊編碼與視訊壓縮,所以在許多多媒體服務中具有極高的應用價值,而在2013年1月25日國際電信聯盟(ITU)推出了新一代的視訊編解碼H.265-HEVC(High Efficiency Video Coding)。
H.265-HEVC是基於H.264-AVC標準,提供了更加靈活、可靠和穩定的視頻處理,在相同的影像品質下,H.265-HEVC的資料量大小約為H.264-AVC的一半,但相對地使用到的技術和演算法更為複雜。
在本論文中主要介紹應用於H.265-HEVC的DCT(discrete cosine transform)與IDCT(Inverse discrete cosine transform),DCT方面是參考[1] Grzegorz Pastuszak(之後以Row/Column DCT表示) 提出的DCT演算法實作出,並且修改其中不合理的部分、IDCT方面則是以Row/Column DCT為基礎修改實作出。
本文依Row/Column DCT演算法做出軟體的正反DCT與硬體的正反DCT獲得的結果數據,在與二維DCT/IDCT軟、硬體的結果數據互相比較,硬體得出的PSNR與軟體結果相差不大,且處理速度獲得大幅的提升。
It is that digital multimedia change the communication and life of human. It has the huge influence on human civilization. Data compression and video encoding are the important technology in the digital multimedia. Because H.264-AVC (Advanced Video Coding) has high efficiency data compression and video encoding, It has the huge influence in many kinds of Multimedia services. The International Telecommunication Union (ITU) has officially agreed on the release of the new video coding standard ITU-T H.265 (HEVC) January 25, 2013.
H.265-HEVC is based on H.264-AVC, but it provides more flexible, more reliable and more stable than H.264-AVC. in the same quality, H.265-HEVC uses half of data volume than H.264-AVC, but H.265-HEVC provides methods and algorithm are more complex than H.264-AVC.
This paper introduce the discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) which applied to H.265-HEVC. Hardware and Software of DCT in this paper is implemented based on the DCT algorithm which is proposed by Grzegorz- Pastuszak and hardware and software of IDCT is implemented based on the modifying Row/Column DCT. Compared the results of data to the traditional software of two-dimensional DCT / IDCT and hardware of two-dimensional DCT / IDCT, performance of PSNR in hardware are not much difference from software, but the processing speed obtain improved dramatically
中文摘要 I
英文摘要 II
誌謝 III
目錄 IV
圖目錄 V
表目錄 VII
第一章 緒論 1
第一節 研究背景與動機 1
第二節 研究方法 5
第三節 論文架構 7
第二章 DCT相關演算法 8
第一節 二維DCT 8
第二節 Row/Column DCT 12
第三章 硬體架構研究方法 17
第一節 二維DCT架構 17
第二節 Row/Column DCT架構 18
第四章 實驗結果 21
第五章 結論 43
[1] Grzegorz Pastuszak,” Hardware architectures for the H.265/HEVC discrete cosine transform”, IET Image Process., 2015, Vol. 9, Iss. 6, pp. 468–477.

[2] Subiman Chatterjee, Kishor Prabhakar Sarawadekar,”A Low Cost, Constant Throughput and Reusable 8X8 DCT Architecture for HEVC”, 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi, UAE.

[3] A. Madisetti and A. N. Willson Jr., “A 100 MHz 2-D 8x8 DCT/IDCT processor for HDTV applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 2, April 1995.

[4] Ricardo Jeske, José Cláudio de Souza Jr., Gustavo Wrege, Ruhan Conceição, Mateus Grellert, Júlio Mattos, Luciano Agostini ,”Low cost and high throughput multiplier less design of a 16 point 1-D DCT of the new HEVC video coding standard”, 978-1-4673-0186-2,©2012 IEEE.

[5] Gary J. Sullivan, Pankaj Topiwala, and Ajay Luthra” The H.264/AVC Advanced Video Coding Standard: Overview and Introduction to the Fidelity Range Extensions”, Presented at the SPIE Conference on Applications of Digital Image Processing XXVII Special Session on Advances in the New Emerging Standard: H.264/AVC, August, 2004

[6] White Paper,” Emerging H.264 Standard: Overview and TMS320C64x Digital Media Platform Implementation”, Copyright © 2002 UB Video Inc.

[7] 楊士萱、陳柏源,” H.264/AVC技術與應用簡介”, 影像與識別 2007

[8] Vojtˇech Holub and Jessica Fridrich,” Low-Complexity Features for JPEG Steganalysis Using Undecimated DCT”, IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY, VOL. 10, NO. 2, FEBRUARY 2015.

[9] Subiman Chatterjee, Kishor Prabhakar Sarawadekar,” A Low Cost, Constant Throughput and Reusable 8X8 DCT Architecture for HEVC”, 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), 16-19 October 2016, Abu Dhabi, UAE.

[10] Edirisuriya, A., Madanayake, A., Cintra, R.J., Bayer, F.M.: ‘Amultiplication-free digital architecture for 16 × 16 2-D DCT/DST transform for HEVC’. Proc. IEEE 27th Conf. of Electrical & Electronics Engineers in Israel, November 2012, pp. 14–17

[11] Chiang, P.-T., Chang, T.S.: ‘A reconfigurable inverse transform architecture design for HEVC decoder’. Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS 2013), May 2013, pp. 1006–1009.

[12] Hatim Anas, Said Belkouch, M. El Aakif, Noureddine Chabini,” FPGA Implementation Of A Pipelined 2D-DCT And Simplified Quantization For Real-Time Applications”, 978-1-61284-732-0, ©2010 IEEE

[13] ITU-T Recommendation H.265 and ISO/IEC 23008-2 MPEG-H Part 2:‘High efficiency video coding (HEVC)’ IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 22, NO. 12, DECEMBER 2012.
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