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研究生:林昱豪
研究生(外文):Yu-Hao Lin
論文名稱:適用於傅立葉轉換之低成本快速數位旋轉器設計
論文名稱(外文):Design of a Low-Cost, High-Speed CORDIC for the Fourier Transform Applications
指導教授:何盈杰
指導教授(外文):Ying-Chieh Ho
學位類別:碩士
校院名稱:國立東華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
論文頁數:54
中文關鍵詞:數位座標旋轉器低功耗傅立葉轉換
外文關鍵詞:CORDIClow powerFourier Transform
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在追求隨時能夠獲取資訊的時代之中,越來越多的手持與穿戴式裝置被發明,攜帶便利為其快速擴展的原因之一,自然地越輕巧的裝置越受人們喜愛,另一個可攜式裝置所被關注的重點為如何增加電池的使用時間,低功率消耗便成為了重要的課題。傅立葉轉換對於可攜式裝置上的語音、影像辨識、頻譜分析,訊號接收傳遞都有卓越的效果。
本論文提出一個可調權重式數位座標旋轉器應用於256點的傅立葉轉換之上,利用可調權重式數位座標旋轉器達成在單一次旋轉中找出符合傅立葉轉換所需要使用到的角度,並搭配上一次的縮放電路處理縮放因子的問題,藉由減少旋轉次數減少來加快電路的操作速度,使用傳輸電晶體邏輯(pass transistor logic)的桶型位移器同時減少位移器的數量藉以節省電路面積功率消耗。本論文所提出之可調權重式數位座標旋轉器之量化訊號雜訊比(Signal-to-Quantization-Noise Ratio, SQNR)平均值為60.58(db),最小值則為48.74(db)。
In the recent era, since there are more and more handheld and wearable devices be developed, people can get information anytime and anywhere. The most important reason for those devices getting popular is convenient to bring up. On the other hand, long time operations in those devices are important issues as well. As a result, reducing power consumptions to allow the devices to be used for longer periods of time is the way we will go on. There are superior efficient that using FFT processor to process voice recognition, image recognition, receive and transfer signals and spectrum analysis in those portable devices.
In the thesis, we proposed a new Reconfigurable Weighting CORDIC applied to 256-point FFT processor. Using the Reconfigurable Weighting CORDIC to achieve the target angle in only one time rotation. In addition, using the one time scaling can deal with the issue of the scaling factor. To be increase the speed of operation, we decrease the times of rotation. At the same time, we used the Barrel Shifter which built with pass transistor logic and also decrease the chip area. According to our proposal, the average SQNR of this Reconfigurable Weighting CORDIC is 60.58(db), and the minimized value is 48.74(db).
摘要 ............................................................I
Abstract .........................................................II
致謝 ..........................................................III
目錄 ...........................................................IV
圖目錄 .........................................................VI
表目錄 .......................................................VIII
第一章 簡介 ......................................................1
1.1 研究背景 .................................................1
1.2 論文大綱 ....................................................3
第二章 數位座標旋轉器相關論文回顧 ..................................5
2.1 簡介 .......................................................5
2.2 傳統數位座標旋轉器(Conventional CORDIC).......................6
2.3 擴展角度數位座標旋轉器(EEAS-CORDIC)...........................8
2.4 混合縮放旋轉數位座標旋轉器(MSR-CORDIC) .......................11
2.5 誤差分析 ..................................................14
2.5.1 量化訊號雜訊比(Signal-to-Quantization-Noise Ratio,SQNR) ..14
第三章 內部電路分析 ..............................................17
3.1 搜索演算法(Searching Algorithm) .............................17
3.1.1 貪婪搜索演算法(Greedy Searching Algorithm) ...............17
3.1.2 全域搜索演算法(Global Searching Algorithm) ...............18
3.2 進位前瞻式加法器(Carry Lookahead Adder, CLA) ................19
3.3 進位儲存加法器(Carry Save Adder, CSA) .......................22
3.4 管線化設計(Pipeline) ........................................24
3.5 預先旋轉(Pre-Rotation) ......................................25
3.6 位移器((Shifter) .........................................25
3.6.1 桶形位移器(Barrel Shifter) ...............................25
第四章 數位座標旋轉器應用於快速傅立葉轉換 ...........................29
4.1 快速傅立葉轉換 ...............................................29
4.1.1 Radix-2 演算法 ...........................................30
4.1.2 Radix-22 演算法 ..........................................32
第五章 低功耗數位座標旋轉器設計 ....................................35
5.1 研究動機 .....................................................35
5.1.1 快速傅立葉轉換所需角度 .....................................35
5.2 架構設計 .................................................39
5.2.1 可移動式架構 ..............................................39
5.2.2 位移器縮減 ................................................40
5.2.3 電路架構分析 ..............................................42
5.2.4 角度誤差 ...............................................43
5.2.5 SQNR比較 ..................................................45
5.2.6 硬體比較 ...............................................46
第六章 晶片合成 .................................................49
第七章 結論及未來方向 ..............................................51
7.1 結論 .........................................................51
7.2 未來方向 .....................................................51
參考文獻 ..........................................................53
1. Volder, J.E., The CORDIC Trigonometric Computing Technique. IRE Transactions on Electronic Computers, 1959. EC-8(3): p. 330-334.
2. Meher, P.K., et al., 50 Years of CORDIC: Algorithms, Architectures, and Applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 2009. 56(9): p. 1893-1907.
3. Hu, Y.H., CORDIC-based VLSI architectures for digital signal processing. IEEE Signal Processing Magazine, 1992. 9(3): p. 16-35.
4. Cheng-Shing, W. and W. An-Yeu. A novel rotational VLSI architecture based on extended elementary angle set CORDIC algorithm. in Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434). 2000.
5. Chih-Hsiu, L. and W. An-Yeu, Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 2005. 52(11): p. 2385-2396.
6. Cheng-Shing, W. and W. An-Yeu, Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2001. 48(6): p. 548-561.
7. Zlatanovici, R., S. Kao, and B. Nikolic, Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example
IEEE Journal of Solid-State Circuits, 2009. 44(2): p. 569-583.


8. Cooley, J.W. and J.W. Tukey, An Algorithm for the Machine Calculation of Complex Fourier Series. Mathematics of Computation, 1965. 19(90): p. 297-301.
9. Shousheng, H. and M. Torkelson. A new approach to pipeline FFT processor. in Proceedings of International Conference on Parallel Processing. 1996.
10. Aggarwal, S., P.K. Meher, and K. Khare, Concept, Design, and Implementation of Reconfigurable CORDIC. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016. 24(4): p. 1588-1592.
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