臺灣博碩士論文加值系統

　　隨著VLSI技術及奈米科技的發展，造成了硬體裝置的縮小、電源供應的降低以及運算頻率的提升，但卻引發了軟錯誤(Soft Errors)，軟錯誤是電路在運算時，線路因為單一事件的不良運作而引起的。例如電子的雜訊或是設計以及製造因素以外的外部輻射所造成的暫時錯誤。這種錯誤會引發功能異常，為了避免在過去的研究指出，可以使用具有自我檢查(Self-Checking)功能的電路可以執行原先具有的功能之外，還可以即時的偵測電路是否發生永久以及暫時的失誤。
　　在本篇論文中，將先敘述對數運算單元是如何運行，並將各運算單元拆成各個小單元來做介紹，本篇論文核心根據共實錯誤偵測(CED，Concurrent Error Detection)方法提出了具有共時錯誤偵測的對數運算器以及以Log為基礎的CED乘法器，其錯誤偵測的功能為偵測兩個相同功能且不同結構的硬體是否會發生兩者為運算結果為不同的情況。
　　在對數轉換公式中採用本實驗室所提出的對數轉換近似方程式[15]與對數反轉換近似方程式[17]當作原型，並推導出具有相同功能且不同架構的方程式並將這些方程式交叉組合測試，同時使用Verilog硬體描述語言來執行模組設計，並使用Synopsys公司的Design Vision TSMC 0.18-μm 進行合成的動作，分析出各種不同架構的方程式，與原著相比我們所推導出來的方程式在Delay相同的情況下可得到5.16%的面積減少，且在ADP的比較下我們的方法減少了9.03%，並且依照此架構完成CED乘法器的分析，在Delay = 10ns時，面積為62772.49444μm2。

　　With the development of VLSI technology and nanotechnology, the hardware device, power supply has been reduced and the operation frequency has been improved. However, soft errors have been occurred, which are that single event occurred in which the circuit is under operation, Such as electronic noise or design and manufacturing factors other than the external radiation caused by the temporary errors.
　　This error can lead to functional anomalies. In order to avoid the fact that in the past studies, it is possible to use a circuit with a self-check (self-test) function to perform the functions already available, and to detect whether the circuit is permanent and temporary Mistakes.
　　In this thesis, we will first describe how the logarithmic computing unit is executed, and the arithmetic unit is split into each smaller unit for introduction. The core of this paper is based on the CED (Concurrent Error Detection) method. A logarithmic processor with total error detection and a logarithmic CED multiplier are been proposed.
　　In the logarithmic conversion formula, the logarithmic conversion approximation equation [15] and the logarithmic inverse transformation approximation equation [17] proposed by our previous work are used as prototypes and the equations with the same function and different architectures are derived. Using the Verilog hardware description language to design the modules and using Synopsys Design Vision TSMC 0.18-μm for synthesizing the equations, different equations of the different
architectures were been analyzed. The derived equations are compared to the original method we can obtain 5.16% area reduction under the same circumstances, and in the ADP (Area Delay Product) reduction can achieve 9.03%. The delay and area of our proposed logarithmic multipliers with CED
ability is 10ns and 62772.49444μm2, respectively.

誌謝 I
摘要 II
Abstract III
目錄 IV
圖目錄 V
表目錄 VI

第一章 緒論 1
1.1動機與目的 2
1.2前人的作法與演變 3
1.3研究工具介紹 4
1.4論文架構 5

第二章 對數算術單元 6
2.1對數算術單元架構 6
2.2對數算數單元之重要性 7
2.3對數轉換器 9

第三章 自我錯誤偵測單元 16
3.1同位檢查加法器 16
3.2複製電路的檢查架構 17

第四章 研究方法 18
4.1對數轉換方法文獻回顧 18
4.2對數轉換器之共時錯誤偵測架構 22
4.3對數轉換近似方程式推導 23
4.4對數轉換器架構 24
4.5對數近似方程式的簡化 25
4.6對數轉換器之面積與延遲的比較與分析 26
4.7對數轉換器之誤差比較與分析 27
4.8對數反轉換器之共時錯誤偵測架構 28
4.9對數反轉換近似方法 29
4.10對數反轉換器之面積與延遲的比較與分析 31

第五章 以對數系統為基礎的CED乘法器設計 32
5.1以對數為基礎之CED乘法器設計 32
5.2 CED乘法器架構分析 35

第六章 結論 36

參考文獻 37

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