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研究生:陳俐卉
研究生(外文):Li-Hui Chen
論文名稱:SOI金氧半場效電晶體於熱載子劣化之電性分析與物理機制研究
論文名稱(外文):Electrical Analysis and Physical Mechanism of Hot Carrier Degradation in SOI MOSFETs
指導教授:張鼎張
指導教授(外文):Ting-Chang Chang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:光電工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:中文
論文頁數:103
中文關鍵詞:熱載子應力劣化電洞注入絕緣層上矽金氧半場效電晶體阻隔金屬矽化層
外文關鍵詞:RPOSOIMOSFETshole injectionhot carrier degradation
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金氧半場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistors, MOSFETs)為積體電路中最重要之電路元件,其具備低製造成本、低功率消耗、易微縮以及在積體電路間有良好之兼容性等優勢。於莫爾定律(Moore’s Law)之微縮效應下,漏電、短通道效應導致閘極控制力下降及功率消耗提高之問題更為顯著。而絕緣層上矽(Silicon On Insulator, SOI)電晶體為追求更高速與省電趨勢下之產物,其性能與可靠度為必須權衡之議題。因此本研究將針對絕緣層上矽金氧半場效電晶體探討其電性分析以及可靠度議題。
第一部分將比較低摻雜汲極區(Lightly Doped Drain, LDD)有無進行鍺之預先非晶化處理之PD-SOI MOSFET,其基本電性及熱載子應力(hot carrier stress, HCS)下之可靠度。此外,本實驗於熱載子應力操作結束之恢復(recover)測試時,臨界電壓(Threshold voltage, VT)以及次臨界擺幅(Subthreshold Swing, S.S.)顯示進一步劣化之異常趨勢。本研究將會藉由改變不同之電性量測手法及量測順序釐清,注入於氧化層之電洞屏蔽部分介面缺陷之影響。並於不同閘極偏壓下之熱載子電應力實驗證實,電洞注入之多寡與閘極及汲極間之偏壓密切相關。
第二部分使用之元件為絕緣層上矽橫向擴散(Lateral diffusion, LD) MOSFETs。相較於一般元件之熱載子應力劣化,劣化程度除了受到汲極工程(drain engineering)之影響,阻障氧化層(Resist Protected Oxide, RPO)之緻密程度竟也與熱載子應力劣化程度互相影響。本研究將藉由半導體模擬軟體ISE-TCAD之電性模擬釐清碰撞游離最嚴重之區域。模擬結果也證實,低N型摻雜之耐壓區(N- drift region)與N+汲極之介面處,電場方向為汲極指向阻障氧化層。因此熱載子應力操作下之元件,阻障氧化層將有明顯載子注入之行為,進而影響元件之電性與可靠度。
Metal-oxide-semiconductor field effect transistor (MOSFET) is the most important device for advanced integrated circuits. The main advantages of a MOSFET are lower fabrication costs per integrated circuits, lower power consumption, easy to scale down and the good compatibility on the ICs. The dimension of MOSFETs had been shrinking continuously by following Moore’s Law, which also leads to excessive leakage current and reliability issues. Silicon-on-insulator (SOI) manufacturing process technology has been developed due to its advantages of low parasitic junction capacitance, low power consumption, and high switching speed. Therefore, we will focus on SOI n-MOSFETs to investigate electrical characteristics and hot carrier reliability issues in this study.
In the first part, we will investigate the electrical analysis and reliability of PD-SOI MOSFET in Lightly Doped Drain(LDD) whether implant the amorphization. Besides, we investigate an abnormal recovery phenomenon induced by hole injection during hot carrier stress. The method by which the hole injection induces the anomalous degradation during recovery can be clarified by different hot carrier stress (HCS) measurement sequences. Owing to this experiment results, the channel surface energy band is drawn down. It’s due to the partial interface defect which caused by the trapped hole will be temporarily shielded during HCS. Furthermore, results of different gate voltage stress experiments indicate that the amount of hole injection is determined by the electric field between the gate and drain.
In the second Lateral Diffused n type MOSFET section, investigates the origin of an abnormal enhancement in on-state current under hot carrier stress (HCS) in n-channel LD SOI-MOSFETs. In general, it is supposed that threshold voltage and subthreshold swing degrade with decreasing current after HCS, the degree to which is dependent on factors in drain engineering. However, this study we will confirm the effect of the density of the resist protect oxide (RPO), which is the blocking layer used for non-salicided area definition, and how it impacts hot carrier degradation. ISE-TCAD simulation results indicate that, at the location of maximum impact-ionization, the direction of the electric field is toward the resist protective oxide (RPO), resulting in hole injection into the RPO during HCS.
目錄
致謝 iii
中文摘要 iv
Abstract vi
目錄 viii
圖目錄 x
表目錄 xiv
第一章 概論 1
1-1前言 1
1-2研究動機 2
第二章 文獻回顧 7
2-1 絕緣層上矽(Silicon On Insulator , SOI)電晶體 7
2-1-1浮體效應(Floating Body Effect , Kink Effect) 8
2-1-2 自熱效應(Self-Heating Effect , SHE) 9
2-2 熱載子效應(Hot Carrier Effect , HCE) 10
2-3 Kirk Effect 11
2-4 短通道效應(Short Channel Effect , SCE) 12
2-4-1臨界電壓下滑(Threshold voltage roll-off) 12
2-4-2 本體碰穿效應(Bulk Punch-Through) 13
2-4-3閘極引發能障下降(Drain Induced Barrier Lowering , DIBL) 13
第三章 參數萃取與量測技術 24
3-1 量測技術 24
3-1-1 電荷充放電技術(Charge pumping) 24
3-1-2 電荷充放電技術的方法與原理 24
3-2 元件參數萃取 26
3-2-1載子遷移率(Carrier Mobility) 27
3-2-2 臨界電壓(Threshold Voltage) 27
3-2-3 次臨界擺幅(Subthreshold Swing) 28
3-3 量測儀器 29
第四章 LDD有無做非晶化處理之於PD-SOI上之熱載子劣化行為比較 33
4.1 簡介 33
4.2實驗架構 34
4.3實驗結果與討論 35
4.3.1基本電性與可靠度之探究 35
4.3.2 HCS後電洞注入之屏蔽效應 36
第五章 PD-SOI LD n-MOSFETs不同RPO緻密程度之元件之熱載子劣化行為比較 51
5.1 簡介 51
5.2實驗架構 52
5.3實驗結果與討論 53
5.3.1 不同緻密程度RPO之SOI n-MOSFETs基本電性比較 53
5.3.2不同緻密程度RPO之SOI n-MOSFETs熱載子效應 57
結論 83
參考文獻 85
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