臺灣博碩士論文加值系統

本論文所研究的是目前在半導體廠常用的高介電係數(High K)材料氧化鉿，作為電阻式記憶體介電層的主要材料，其特性穩定且匹配半導體製程，故選擇此材料作為研究對象。RRAM元件的崩潰電壓(forming voltage)會隨著元件尺寸(Via Size)縮小而上升，此現象對於未來RRAM元件的微縮應用不利。
為了解決此問題，本研究設計出一種新型RRAM結構，在原有的MIM堆疊層，在側壁增加一層氧化鉿的材料，通過將電場集中於切換層，藉此減緩崩潰電壓(forming voltage)會隨著元件尺寸(Via Size)縮小而上升的現象。但除此之外，我發現新結構在電性方面與傳統SiO2側壁有所不同，在Set過程，當儀器限流值升高，將使Reset達到電阻值更高的高電阻態；在耐久度的測試中，HRS阻值會隨著操作次數增加而上升，我們認為是大量氧離子與阻絲反應所造成。因此增加一層C:BN，抓住氧離子成功增加元件的耐久度。
RRAM在reset時因升壓時間快慢，可分為電場效應及熱效應。高介電系數側壁，能增加電場效應影響，控制更多氧離子達到高的阻值；低熱傳導係數側壁，將熱保存活化氧離子與阻絲反應，得到高的阻值。

We find that the forming voltage will become larger when the cell size is scale down which might deter the real applications for RRAM devices. A method is proposed to solve this problem by means of side-wall structure modification in RRAM devices. Experimental results show that the device with modified side-wall can effectively suppress the forming voltage rising within small via size RRAM devices. Moreover, we also observe the ratio of high and low resistance state become larger by increasing SET current compliance, comparing to the traditional SiO2 side-wall devices. In the endurance test, HRS resistance increases when adding the number of operations. We conclude that the reason is because large number of oxygen ions participate the reaction with filament. Thus, a C:BN layer was inserted to suppress the reaction of oxygen ions to further enhance the reliability of devices.
Both electric field effect and thermal effect were found to dramatically affect RRAM characteristics. As a result, a high-k side wall structure in RRAM can enhance the impact of electric field effect. In addition, RRAM with the low thermal conductivity coefficient side wall can preserve thermal energy to activate oxygen ions reacting with filament to attain higher resistance of HRS.

目錄
論文審定書 i
致謝 iii
摘要 iv
Abstract v
目錄 vi
圖次 x
表次 xv
第一章 序論 1
1-1前言 1
1-2研究目的與動機 2
第二章 文獻回顧 4
2-1次世代非揮發性記憶體 4
2-1-1 鐵電式隨機存取記憶體(FeRAM) 4
2-1-2 磁阻式記憶體(MRAM) 5
2-1-3 相變化記憶體(PCRAM) 6
2-1-4 電阻式記憶體(RRAM) 6
2-2電阻式記憶體接換機制 8
2-2-1 阻絲理論(Filament-type theory) 8
2-2-2 介面效應 (Interface-type theory) 10
2-3.絕緣體載子傳導機制 10
2-3-1 歐姆傳導(Ohmic conduction) 11
2-3-2 蕭基發射(Schottky emission 12
2-3-3 普爾-法蘭克發射(Poole-Frenkel emission) 13
2-3-4 躍遷傳導機制(Hopping conduction) 14
2-3-5 穿隧效應 (Tunneling) 15
2-3-6 空間電荷限制電流(Space charge limited current) 16
第三章 實驗設備 18
3-1製程設備 18
3-1-1 多靶磁控濺鍍系統 (Multi-Target Sputter) 18
3-1-2 感應耦合式電漿蝕刻系統(Inductive Couple Plasma Etcher) 19
3-2材料分析設備 20
3-2-1 傅立葉轉換紅外光譜儀 (Fourier-Transform Infrared Spectrometer) 20
3-2-2 X 光電子能譜 (XPS) 22
3-2-3 N&K薄膜特性分析儀 (N & K Analyzer) 23
3-2-4 雙束型聚焦離子束(Focus Ion Beam) 23
3-2-5穿透式電子顯微鏡(Transmission Electron Microscopy) 24
3-3電性量測設備 25
3-3-1 半導體精準電性量測系統 25
第四章 氧化鉿電阻式記憶體受脈衝劣化切換之機制研究 28
4-1 氧化鉿電阻式記憶體製作流程 28
4-1-1氧化鉿薄膜備製 29
4-1-2白金上電極製備 29
4-2氧化鉿薄膜材料分析 30
4-2-1 FTIR化學定性分析 30
4-2-2 XPS化學定量分析 30
4-3氧化鉿薄膜元件電性分析比較 31
4-3-1氧化鉿薄膜元件I-V基本特性及確認漏電機制 31
4-4氧化鉿薄膜元件可靠度分析 34
4-4-1氧化鉿薄膜元件可靠度 34
4-4-2 60℃下endurance測試 38
4-4-3 氧化鉿元件受脈衝切換劣化模型 38
第五章 High K側壁結構對氧化鉿電阻式記憶體之影響與研究 41
5-1氧化鉿側壁結構電阻式記憶體 (HfO2 side-wall RRAM) 41
5-1-1 HfO2 side-wall結構製備 41
5-1-2 Si:HfO2薄膜製備 43
5-1-3白金上電極備製 44
5-2氧化鉿側壁及氧化鉿參雜矽薄膜材料分析 45
5-2-1 FTIR化學定性分析 45
5-2-2 XPS化學定量分析 46
5-2-3 HfO2 side-wall TEM分析 48
5-3 HfO2 side-wall與SiO2 side-wall RRAM forming分析 48
5-3-1不同Via-Size Forming mapping 48
5-4 HfO2 side-wall結構與SiO2 side-wall RRAM基本特性分析 49
5-4-1 HfO2 side-wall RRAM I-V基本特性及確認漏電機制 49
5-4-2 SiO2 side-wall結構RRAM I-V基本特性及確認漏電機制 52
5-4-3 HfO2 side-wall及SiO2 side-wall RRAM不同set限流操作比較 54
5-4-4改變Set能量對HfO2 side-wall及SiO2 side-wall RRAM reset影響 57
5-4-5氧化鉿側壁結構元件急遽Reset模型 60
5-5 HfO2 side-wall結構與SiO2 side-wall RRAM可靠度分析 62
5-5-1 SiO2 side-wall RRAM endurance測試 62
5-5-2 HfO2 side-wall RRAM endurance測試 63
5-5-3 HfO2 side-wall RRAM endurance劣化模型 64
第六章 C:BN side-wall與double layer side-wall RRAM 可靠度分析 65
6-1 C:BN side-wall與double layer side-wall RRAM元件製備 65
6-1-1 C:BN side-wall製備 65
6-1-2 C:BN/HfO2及HfO2/C:BN side-wall製備 66
6-1-3 Si:HfO2薄膜製備 66
6-1-4白金上電極備製 66
6-2 C:BN side-wall材料分析 67
6-2-1 FTIR化學定性分析 67
6-2-2 XPS化學定量分析 68
6-3 C:BN side-wall結構與C:BN/HfO2(HfO2/C:BN) side-wall RRAM基本特性分析 69
6-3-1不同Via-Size Forming mapping 69
6-3-2 C:BN side-wall及兩種double layer side-wall RRAM漏電機制分析 70
6-4 C:BN/HfO2 side-wall RRAM endurance測試 72
6-5 C:BN side-wall與HfO2/C:BN side-wall RRAM endurance測試 73
6-6 C:BN與HfO2 Side-wall對於RRAM endurance影響 73
第七章 Side-wall材料對於電場效應及熱效應影響 75
7-1 電場效應及熱效應 75
7-2 Side-wall 介電系數與熱傳導係數 76
7-3 Side-wall對電場效應影響 77
7-4 Side-wall對熱效應影響 80
第八章 結論 83
參考文獻 84

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