臺灣博碩士論文加值系統

矽基板佔矽晶太陽能電池成本的40%，若能製作出超薄矽晶太陽能電池，則可降低太陽能電池的成本，更有機會發展可撓性的應用。然而受限於矽晶的光吸收特性，其厚度小於50μm時會有高於 23 %的太陽光無法被吸收發電。本研究即以光吸收係數高達10∧5/cm的CuInSe2(簡稱CIS)薄膜結合超薄Si同質接面(Homojunction)成為新型元件結構以解決上述問題，並探討CIS/Si界面改質方法對元件發電特性的影響。這項研究主要以PC-1D太陽電池元件模擬程式代入各方實驗室測得的材料性質參數進行運算，並利用Taguchi法進行元件優化。由於晶矽與CIS的晶格不匹配程度過高，導致界面複合速率高達4.79x10∧5 cm/s，故而當矽基板厚度為10μm時，其元件發電效率僅為18.9% (Voc=0.673V, Isc=33.5mA, FF=83.8%)。在界面改質方面，先以氫化非晶矽或氫化非晶鍺進行界面鈍化，並用具多晶結構的CIS為吸收層。然而其元件發電效率相較於上述元件僅提升不到2%，主要歸因於多晶CIS之材料性質遜於單晶者(多晶CIS的光吸收係數為10∧4/cm，僅有單晶CIS的1/10；而在載子濃度同為1x10∧19 holes/cm3之下，多晶CIS之擴散長度為200nm，是單晶CIS的1/15)。接著，試以凡德瓦爾磊晶法在Si與CIS之間置入具二維材料結構的InSe半導體膜層以隔斷界面差排的出現，因InSe在元件能帶結構的導帶和價帶不連續位置產生的落差不一，其能障可導致電子與電洞的分離，以至於在元件結構中呈現有如雙電池堆曡串聯的效果。當前最佳化的元件結構為n-Si(100nm)/p-Si(5μm)/ p-InSe(20nm)/p-CIS(1700nm)，其模擬結果顯示該元件結構其發電效率可達32.5% (Voc=0.781V, Isc=50.9mA, FF=81.8%)。

The cost analysis of a crystalline Si solar cell indicates a considerable cost percentage belonging to the Si wafer. The advantages to use ultrathin Si wafers (5 ~ 50 μm in thickness) not only cut down the material cost but also extend its application on BIPV due to the flexibility of final product. A reduction in the wafer thickness may cause a significant loss of light absorption in Si. In this work, an efficient light absorber of CuInSe2 (CIS) with an optical coefficient as high as 10∧5 /cm is attached to the bottom of a Si homojunction to form a novel device structure of n-Si/p-Si/p-CIS. We perform the device simulation study by using PC-1D simulation tool along with the experimental data of material parameters acquired from the literature survey. Furthermore, Taguchi method has been applied to help optimizing the device performance. Since a large lattice mismatch between Si and CIS causes high surface recombination velocity of 4.79x10∧5 cm/s at the interface, an energy conversion efficiency of 18.9% (Voc=0.637V, Isc=33.5mA, FF=83.8%) is obtained. Modification of interfacial structure through the incorporation of a hydrogenated amorphous Si or Ge film at the Si/CIS interface has been proposed but the improvement in the energy conversion efficiency limited to only about 2%. It is attributed to the inferior properties of polycrystalline CIS as compared with those of single-crystalline CIS. Another way proposed for interface modification is the use of Van der Waals Epitaxy, i.e. a thin layer of 2D material such as InSe is inserted between Si and CIS in order to prohibit the formation of misfit dislocations at the interface. There exist the discontinuity of conduction band and valence band with different values at the Si/CIS interface, which in turn may separate the electrons and holes generated in CIS after light absorption. This leads to a tandem-cell behavior in our device. With a proper adjustment of device parameters, a device structure of n-Si(100nm)/p-Si(5μm)/p-InSe(20nm)/p-CIS(1700nm) may reach an energy conversion efficiency of 32.5% (Voc=0.781V, Isc=50.9mA, FF=81.8%).

論文審定書 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vii
表目錄 ix

第一章 緒論 1
1-1 前言 1
1-2 矽晶太陽能電池 4
1-3 CuInSe2材料基本性質 8
1-4研究動機與目的 13
第二章 PC1D 之介紹 15
2-1 PC1D介紹 15
2-2 PC1D之基礎方程式 15
2-2-1 載子傳輸(transport) 15
2-2-2 帶電載子分佈統計學(載子密度) 16
2-2-3 連續方程式 17
2-2-4 波松方程式(Poisson’s equation) 18
2-2-5 邊界條件 19
2-3 PC1D之物理模型 20
2-3-1 折射率(index of refraction) 20
2-3-2 光吸收係數(optical absorption coefficient) 21
2-3-3 自由載子吸收(Free-carrier absorption) 22
2-3-4 電容率(Permitivity) 23
2-3-5 能帶結構(band structure) 23
2-3-6 能帶窄化(Bandgap narrowing)(BGN) 24
2-3-7 遷移率(Mobility) 25
2-3-8 載子復合(recombination) 26
2-3-9 未完全游離的摻雜(Incomplete ionization) 27
第三章 Si-CIS元件設計與模擬結果 28
3-1 P-N單晶矽元件設計與模擬 28
3-1-1 PERL之模擬 29
3-1-2 單晶矽厚度與摻雜濃度 30
3-1-3 PN接面深度與摻雜濃度 32
3-1-4 P-N單晶矽之模擬結果 32
3-2 Si-CIS元件設計 34
3-2-1 界面與表面之復合速率 35
3-2-2 CIS載子濃度與遷移率之關係 36
3-2-3以田口法分析SiCIS之模擬結果與討論 38
3-2-4 CIS厚度對SiCIS元件效率之影響 43
3-2-5 CIS載子濃度對SiCIS元件效率之影響 45
3-2-6界面復合速率對SiCIS元件效率之影響 46
第四章 以非晶矽或非晶鍺鈍化界面之設計與模擬結果 47
4-1多晶CIS之材料引用 47
4-1-1 多晶CIS材料基本性質 47
4-1-2 多晶CIS載子濃度與遷移率之關係 48
4-2以非晶矽鈍化界面層之元件設計與模擬 50
4-2-1 非晶矽之材料參數 50
4-2-2 以田口法分析元件之模擬結果與討論 51
4-2-3 多晶CIS載子濃度對元件效率之影響 55
4-3以非晶鍺鈍化界面層之元件設計與模擬 56
4-3-1 非晶鍺之材料參數 56
4-3-2 以田口法分析元件之模擬結果與討論 57
4-3-3非晶鍺厚度對元件效率之影響 61
4-4以非晶材料鈍化界面之結論 63
第五章 以凡德瓦爾磊晶鈍化界面之設計與模擬結果 64
5-1以InSe鈍化界面之元件設計 64
5-1-1 InSe之材料參數 64
5-1-2 InSe載子濃度與載子遷移率之關係 65
5-2元件設計之模擬結果 67
5-2-1 以田口法分析元件之模擬結果與討論 67
5-2-2 矽基板厚度與元件效率之討論 70
5-2-3 CIS與InSe載子濃度對元件效率之影響 73
5-2-4 InSe與CIS厚度對元件效率之影響 75
5-2-5 減薄矽基板厚度對元件表現之影響 77
5-2-6元件之結論 78
第六章 結論 80
第七章 參考文獻 82

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