臺灣博碩士論文加值系統

嵌入式電腦視覺應用講求著快速、即時且低功耗的限制，面臨這些挑戰需要的是更適合影像處理的專屬硬體，並希望保持可程式化的彈性。本論文提出了一基於OpenVX標準之視覺處理器，以SIMD(single instruction multiple data)的處理器陣列為核心架構，並以自定之指令集架構來組合，利用這些指令間不同的組合來實現OpenVX所提出的視覺函數，達到快速即時且低功耗的影像處理目標。

Embedded computer vision applications emphasizes fast and real-time processing speed with low power consumption. To face these challenge, we need more suitable hardware accelerator for image/vision processing with more programmability. This thesis proposes a vision processor based on the OpenVX specification. The architecture includes a column of processing elements (Pes) forming an SIMD processor array with full-custom instruction set. The proposed vision processor can perform the basic low-level visual function API defined in the OpenVX.

中文摘要 ii
Abstract iii
第1章 導論 1
1.1 研究動機 1
1.2 論文組織 1
第2章 相關文獻 2
2.1 OpenVX API 標準 2
2.1.1 OpenVX API概述 3
2.1.2 OpenVX視覺函數 4
2.2 視覺處理器 6
2.2.1 通用視覺處理器 6
第3章 OpenVX視覺處理器 10
3.1 處理器架構簡述 10
3.2 指令集 11
3.2.1 指令集設計 11
3.2.2 用指令集來組成OpenVX API 13
3.3 OpenVX視覺處理器資料流程 16
第4章 硬體設計 18
4.1 處理單元設計 18
4.1.1 SIMD處理器陣列 19
4.1.2 可重建之處理單元 20
4.2 控制單元設計 22
4.3 資料傳送單元和影像記憶體設計 23
4.3.1 資料傳輸單元 23
4.3.2 影像記憶體設計 24
4.4 管線化 26
第5章 測試數據與分析 28
5.1 合成數據 28
5.2 API測試圖 30
第6章 結論與未來目標 32
6.1 結論 32
6.2 未來目標 33
參考文獻 34
附錄A(Appendix A) 37

[1]Khronos Group, “The OpenVX provisional specification vision1.0.1” https://www. Khronos.Org/openvx.
[2]S. Kyo, S. Okazaki, and T. Arai, “An integrated memory array processor for embedded image recognition systems,” IEEE Trans. Comput., vol. 56, no. 5, May 2007, pp. 622–634
[3]P.P. Jonker, “Why Linear Arrays Are Better Image Processors,” Proc. IAPR Conf. Pattern Recognition, vol. 3, 1994 , pp. 334-338
[4]W. Zhang, Q. Fu, and N. Wu, “A programmable vision chip based on multiple levels of parallel processors,” IEEE J. Solid-State Circuits, vol. 46, no. 97, Sep. 2011. , pp. 2132–214
[5]A. Neito, D. Vilarino, V. Brea " PRECISION: A reconfigurable SIMD/MIMD coprocessor for Computer Vision Systems-on-Chip," IEEE Transactions on Computers, 2015, pp. 1-1.
[6]J. S. Yoon, J. H. Kim, H.E. Kim, W. Y. Lee, S. H. Kim, K. Chung, J.S. Park, L.S. Kim, “A Unified Graphics and Vision Processor With a 0.89 W/fps Pose Estimation Engine for Augmented Reality, ” IEEE Transactions on Very Large Scale Integration System, vol. 21,no. 2, 2013, pp. 206-216
[7]A. Abbbo, R. Kleihorst, V. Choudhary, L. Stevat, P. Wielage, S. Mouy, M. Heijligers, “XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis, ” ISSCC Dig. Tech. papers, vol. 1, 2007, pp. 270-271
[8]黃冠潣, “同時支援浮點數和定點格式運算之可程式化頂點處理器設計、實做與驗證”,國立中山大學資訊工程學系碩士論文,July,2009
 
[9]A. Nieto; D. L. Vilariño; V. M. Brea “SIMD/MIMD Dynamically-Reconfigurable Architecture for High-Performance Embedded Vision Systems, ” IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, 2012, pp. 94-101
[10]Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa “Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture, ” IEEE International Symposium on Circuits and Systems, 2007, pp. 3498-3501
[11]Chih-Chi Cheng; Chia-Hua Lin; Chung-Te Li; Samuel C. Chang; Liang-Gee Chen “iVisual: An intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor,” IEEE Conference Publications, 2008, pp. 90-95.
[12]Shorin Kyo; Shin''ichiro Okazaki; Takuya Koga; Fumiyuki Hidano “A 100 GOPS in-vehicle vision processor for pre-crash safety systems based on a ring connected 128 4-Way VLIW processing elements,’’ IEEE Symposium on VLSI Circuits, 2008, pp. 28-29
[13]A. Nieto; D. L. Vilariño; V. M. Brea “SIMD/MIMD Dynamically-Reconfigurable Architecture for High-Performance Embedded Vision Systems,’’ IEEE Transactions on Computers, 2012, pp. 94-101
[14]Joseph A. Schmitz; Mahir Kabeer Gharzai; Sina Balkır; Michael W. Hoffman; Daniel J. White; Nathan Schemm “A Programmable Vision Chip with Pixel-Neighborhood Level Parallel Processing,’’ IEEE International Symposium on Circuits and Systems, 2015, pp. 2125-2128
[15]Cong Shi; Jie Yang; Ye Han; Zhongxiang Cao; Qi Qin; Liyuan Liu; Nan-Jian Wu; Zhihua Wang “A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network,’’ IEEE Journal of Solid-State Circuits, 2014, pp. 2067-2082
[16]V. Cantoni; L. Lombardi “Hierarchical architectures for computer vision,’’ Proc. Euromicro Workshop Parallel and Distributed Processing, 1995, pp. 392-398