臺灣博碩士論文加值系統

本論文使用 TSMC 90nm 製程技術，提出一個操作電壓在 0.5V，取樣頻率每秒五十萬次、十位元應用於生物訊號的逐漸逼近式類比數位轉換器。本文提出之設計將應用於物聯網相關的感測器與感測器電路，此設計可以達到低成本與低 功耗的目標。
在逐漸逼近式類比數位轉換器設計中，為了使效能提升並且降低電容陣列功率消耗，因此採用了拆分合併的電路架構。另外也採用動態比較器技術，以減少靜態功率消耗。為了使電路更快進入比較狀態，在拆分合併架構中將多設計一組開關，使電壓能更快趨於穩定狀態。本文中採用拆分合併架構的切換方法，其電容陣列的能量消耗只比單調式架構略少一點，探究其原因，發現電容陣列在重置過程中的能量消耗過大。因此為了減少拆分合併架構的重置消耗功率，對電容陣 列重新調整。設計方法為，將電容陣列中最大的電容移除，也就是使用 N-1 位 元的電路架構，實現 N 位元電路架構的功能，優點在於可以降低一半的重置消 耗功率。為了達到 N-1 位元轉 N 位元的方法，設計兩組三級切換開關，使電 容陣列中的 Cf 可以進行運算，進而達到降低功率消耗的目的。
最終本論文提出一個輸入訊號為 500Ks/s，SNDR 為 53.384 dB，有效位元 數為 8.575 位元，微分非線性誤差 (DNL) 為 0.373/-1.0 LSB，積分非線性誤差 (INL) 為 1.922/-2.098 LSB。所消耗的功率為 1.4261 µW，晶片佈局面積為 0.5665 mm × 0.55 mm。

This thesis presents a 10-bit 500KS/s Successive Approximation Analog-to-Digital Converter (SAR ADC) for biomedical applications with a 0.5 V supply voltage which is implemented by using TSMC 90nm process technology. The proposed in this paper will be applied to the sensors and sensor circuits related to the Internet-of-Things (IoT). This design can achieve the purpose of low cost and low power. In the SAR ADC design in order to improve performance and reduce DAC switching energy, so we use the merge and split (MS) switching architecture. In addition dynamic comparator technology is also used to reduce static power consumption. In order to make the circuit faster to enter the comparison state, so in the MS architecture will be more design a group of switches, so that the voltage can be more quickly stabilized. In this thesis, the DAC switching energy is only slightly less than that of the monotonic, It is found that the reset energy of the DAC switching energy is too large in the reconstruction process. Therefore, to reduce the MS reset energy, we re-adjust for the capacitor array. The design approach is to remove the maximum capacitance of the capacitor array that is to use the N-1 bit architecture to transfer the function of N bit architecture, the advantage is that can reduce the energy of half of the reproduction. In order to achieve N-1 bit transfer N-bit method, the design of two groups of Tri-level switching, so that the capacitor array Cf can be calculated, and thus to reduce power consumption purposes. When sampling rate is 500KS/s, the SNDR is 53.384 dB, and ENOB is 8.575 bit. DNL and INL are 0.373/-1.0 LSB and 1.922/-2.098 LSB. The power consumption is 1.4261 µW, and the chip area is 0.5665 mm × 0.55 mm

目錄
論文審定書 ............................................................................................................ i
摘 要...................................................................................................................... ii
ABSTRACT .................................................................................................................. iii
目錄................................................................................................................................ iv
圖目錄........................................................................................................................ vii
表目錄........................................................................................................................... x
第 1 章 緒論.................................................................................................................. 1
1.1 研究動機與目標 ........................................................................................... 1
1.2 論文組織架構 ............................................................................................... 4
第 2 章 類比數位轉換器基本原理介紹...................................................................... 5
2.1 常見的類比數位轉換器架構 ....................................................................... 5
2.1.1 快閃式類比數位轉換器(Flash ADC) .................................................. 5
2.1.2 兩階段類比數位轉換器(Two-step ADC) ............................................ 6
2.1.3 管線式類比數位轉換器(Pipeline ADC) .............................................. 7
2.2 逐漸逼近式類比數位轉換器架構 (Successive Approximation ADC) ...... 9
2.2.1 傳統式類比數位轉換器(Conventional SAR ADC) ........................... 11
2.2.2 單調式類比數位轉換器(Monotonic SAR ADC) ............................... 13
2.2.3 平均充電式類比數位轉換器(Charge-Average Switching SAR ADC) 14
2.2.4 拆分合併式類比數位轉換器(Merge and Split SAR ADC) .............. 16
2.3 類比數位轉換器的特性參數 ..................................................................... 19
2.3.1 最小有效位元(Least Signification Bit) .............................................. 19
2.3.2 量化誤差(Quantization Error) ............................................................ 19
2.3.3 單一性(Monotonicity) ........................................................................ 19
2.3.4 靜態性能參數 ..................................................................................... 20
2.3.4.1 微分非線性度誤差(Differential Nonlinearity, DNL) ................ 20
2.3.4.2 積分非線性度誤差(Integral Non-Linearity, INL) ..................... 21
2.3.4.3 遺失碼(Missing Code) ............................................................... 22
2.3.4.4 偏移誤差與增益誤差(Offset and Gain Error) ........................... 22
2.3.5 動態性能參數 ..................................................................................... 24
2.3.5.1 訊號雜訊比(Signal-to-Noise Ratio, SNR) ................................. 24
2.3.5.2 訊號雜訊失真比(Signal-to-Noise & Distortion Ratio, SNDR) . 24
2.3.5.3 無寄生動態範圍(Spurious Free Dynamic Range, SFDR) ......... 24
2.3.5.4 有效位元(Effective Number of Bits, ENOB) ............................ 25
第 3 章 低功率類比數位轉換器電路設計................................................................ 26
3.1 設計考量 ..................................................................................................... 26
3.2 參考電路之電容陣列 ................................................................................. 26
3.2.1 單調式電容陣列 ................................................................................. 26
3.2.2 拆分單調式電容陣列 ......................................................................... 30
3.2.3 拆分合併式開關之電容陣列 ............................................................. 32
3.2.4 提出拆分合併式與三級開關之電容陣列 ......................................... 35
3.3 切換能量分析 ............................................................................................. 37
3.3.1 電容陣列開關能量分析 ..................................................................... 37
3.3.2 提出之架構開關能量分析 ................................................................. 38
第 4 章 類比數位轉換器系統實現............................................................................ 43
4.1 取樣保持電路(Sample and hold circuit, S/H) ............................................ 47
4.1.1 電阻值設計考量 ................................................................................. 48
4.1.2 拔靴式開關 (Bootstrapped Switch) ................................................... 48
4.2 比較器電路(Comparator) ........................................................................... 53
4.3 逐漸逼近暫存器邏輯控制電路(Successive Approximation Register logic, SAR Control logic) ..................................................................................... 55
4.4 電容與電容陣列電路佈局設計 ................................................................. 58
4.4.1 MOS 電容 .......................................................................................... 58
4.4.2 MIM 電容 .......................................................................................... 58
4.4.3 MOM 電容 ......................................................................................... 59
4.4.4 電容陣列設計 ..................................................................................... 60
4.5 類比數位轉換器全電路之佈局 ................................................................. 62
第 5 章 效能與模擬結果............................................................................................ 66
5.1 效能測試方法-FFT test .............................................................................. 66
5.2 模擬結果與比較 ......................................................................................... 68
5.2.1 靜態分析 ............................................................................................. 69
5.2.2 動態分析 ............................................................................................. 73
第 6 章 結論................................................................................................................ 76
6.1 結論 ............................................................................................................. 76
6.2 未來展望與待改進之處 ............................................................................. 76
6.2.1 未來展望 ............................................................................................. 77
6.2.2 待改進之處 ......................................................................................... 77
參考文獻...................................................................................................................... 81

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