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研究生:王令羽
研究生(外文):Ling-yu Wang
論文名稱:基於可重複定義晶片匯流排監控硬體之整合設計環境
論文名稱(外文):Integration design environment for configurable on-chip bus monitor
指導教授:黃英哲黃英哲引用關係
指導教授(外文):Ing-Jer Huang
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:84
中文關鍵詞:自動化效能監測協定監測可重複定義
外文關鍵詞:AutomaticallyReconfigurableProtocol MonitorPerformance Monitor
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因為現今的製程技術越來越進步,單一晶片中所能容納的Intellectual Property (IP)數量越來越多,在IP大量增加的情況下,晶片上匯流排中IP之間的傳輸會變得更為複雜,造成晶片的驗證與除錯之困難度提高。而就算於RTL階段模擬並驗證完硬體,還是會有部分錯誤在晶片產出之後產生,因此硬體產出後的除錯及監控也是系統晶片設計上重要的一環。以往的硬體監控器所能監控的條件是有限的,若測試者想監控其他的條件行為,必須更換硬體監控器抑或是加入更多硬體,這會大大提升硬體設計的成本。我們所提出的可重複定義之硬體監控器(Reconfigurable Bus Monitor)便是要解決此問題,達到可重複定義監控條件的功能來降低硬體設計成本。然而過多的彈性化設計會造成RBM的面積過大,因此我們結合了內部的檢查器並提出一個斷言分派演算法來幫助使用者產出在面積上優化的RBM。這篇論文所提出的方法在RBM的硬體成本及彈性之間找到一個較好的平衡。
Nowadays, because the advance of the technology, a single chip can contain more and more Intellectual Property(IP). As the design increase with the IPs from different designer, intercommunication in System-on-Chip(SoC) becomes more complicated and rarely error-free. This cause the verification and integration more difficult. Although RTL simulation is error-free, there may also have some bug on FPGA or post-silicon. It is important to focus on the monitor and debug method while designing the chip. The monitor is hard-wired in the chip that cannot be changed. We must replace the monitor or add more hardware if the designer wants to monitor other rules or condition. It may cause the hardware cost increase or need unrealistic change. Therefore, we have proposed a Reconfigurable Bus Monitor (RBM) to solve this problem. With the reconfigurable ability to decrease the cost of hardware design. However, the flexibility will also cause a huge area cost. Therefore, we combine the rule checking result inside the RBM and proposed an assertion analysis algorithm to help debugger to generate RBM which has more optimize area cost. The proposed method get the balance between hardware area cost and debugging time.
論文審定書 i
中文摘要 iii
Abstract iv
Contents v
List of Figures viii
List of Tables xi
Chapter 1. Introduction 1
1.1 Background 1
1.2 Motivation 3
1.3 Organization of the Thesis 5
Chapter 2. Related Works 6
2.1 Multiplexed Signal Tracing 7
2.2 Rule-based protocol checker 8
2.3 Synthesizable assertion checker 9
2.4 Performance Monitor 11
2.5 Security Monitor 12
2.6 Distributed monitor 14
2.7 Mapping Trigger Conditions 16
2.8 Problem Discussions 18
Chapter 3. Reconfigurable Bus Monitor 19
3.1 Signal Selection Module 21
3.2 Event Generation Module 23
3.3 Event Combination Module 25
3.4 Event Sequencing Module 27
3.5 Status controller 29
3.6 RBM expression 30
Chapter 4. Extensive Methodology 31
4.1 Problem on RBM 31
4.2 Combination of rule result 34
4.3 Example of using Extended method 37
4.3.1 Multiple debug sessions 37
4.4 Rule analyzing algorithm 38
4.5 Extend RBM IDE with rule patching method 48
4.5.1 How to generate signal checking result 50
4.5.2 Patching rule into RBM 51
4.5.3 Rule patching algorithm 55
4.5.4 RBM generator interface 58
4.5.5 Generating RBM for different BUS architecture 61
Chapter 5. Experimental Result 62
5.1 Result of rule analyzing algorithm 64
5.1.1 If PM is bigger than checher 65
5.1.2 Multiple debug session 65
Chapter 6. Conclusion 66
Chapter 7. Future Work 67
7.1 Wiring complexity 67
7.2 Access by other program 67
7.3 Cooperate with SBICE 68
References 69
Appendix A : Security Monitor 70
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[10]Boule, Marc, and Zeljko Zilic. "Efficient automata-based assertion-checker synthesis of SEREs for hardware emulation." Proceedings of the 2007 Asia and South Pacific Design Automation Conference. IEEE Computer Society, 2007.
[11]Boulé, Marc, Jean-Samuel Chenard, and Zeljko Zilic. "Adding debug enhancements to assertion checkers for hardware emulation and silicon debug." Computer Design, 2006. ICCD 2006. International Conference on. IEEE, 2007.
[12]Boulé, Marc, and Zeljko Zilic. "Automata-based assertion-checker synthesis of PSL properties." ACM Transactions on Design Automation of Electronic Systems (TODAES) 13.1 (2008): 4.
[13]Mohamad, Nurita, et al. "SVA checker generator for FPGA-based verification platform." Circuits and Systems (ISCAS), 2016 IEEE International Symposium on. IEEE, 2016.
[14]Kyung, Hyun-min, et al. "Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)." Microprocessors and Microsystems 34.2 (2010): 102-116.
[15]Chang, Yi-Hao, et al. "A performance monitoring tool suite for 3D graphics SoC application." Circuits and Systems (APCCAS), 2012 IEEE Asia Pacific Conference on. IEEE, 2012.
[16]Todman, Tim, Stephan Stilkerich, and Wayne Luk. "In-circuit temporal monitors for runtime verification of reconfigurable designs." Proceedings of the 52nd annual design automation conference. ACM, 2015.
[17]Alsaiari, Uthman, Fayez Gebali, and Mostafa Abd-El-Barr. "Programmable assertion checkers for hardware Trojan detection." PhD Research in Microelectronics and Electronics Latin America (PRIME-LA). IEEE, 2017.
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[19]Backer, Jerry, David Hély, and Ramesh Karri. "On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks." Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on. IEEE, 2015.
[20]Xilinx ChipScope Pro 12.3 Software and Cores, 2010.
[21]ARM ® DS-5™ Version 5.18 Debugger User Guide, 2010.
[22]UltraSoC, Available: http://www.ultrasoc.com/
[23]Ko, Ho Fai, and Nicola Nicolici. "Automated trace signals identification and state restoration for improving observability in post-silicon validation." Proceedings of the conference on Design, automation and test in Europe. ACM, 2008.
[24]Larsson, Erik, Bart Vermeulen, and Kees Goossens. "A distributed architecture to check global properties for post-silicon debug." Test Symposium (ETS), 2010 15th IEEE European. IEEE, 2010.
[25]Ko, Ho Fai, and Nicola Nicolici. "Mapping trigger conditions onto trigger units during post-silicon validation and debugging." IEEE Transactions on Computers 61.11 (2012): 1563-1575.
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