臺灣博碩士論文加值系統

本論文提出一新型交錯式倍壓升壓型轉換器，並以數位式平均電流控制法達成功率因數修正。本文所提之電路架構利用雙相交錯式架構，減少元件上的電流應力與電磁干擾問題，此外為了應用於高電壓場合，電路架構於輸出端使用兩電容疊加成倍壓電路，利用雙相交錯式操作對兩電容交替充電，使其輸出電壓增益，可達一般升壓型轉換器的兩倍，此外，所提架構更能減少功率開關所承受的電壓應力。本文所提出之交錯式倍壓升壓型轉換器可藉由繼電器切換調整為單相架構操作，此時之電壓增益與一般升壓型轉換器相同，但透過交錯式雙相操作與單相操作的搭配，可實現更大範圍的輸出電壓變動，以提供較大的運用彈性。本文中利用TI TMS320F28335數位訊號處理晶片，實現一交流輸入電壓110V，直流輸出電壓200V至700V及輸出功率700W之交錯式倍壓升壓型功率因數修正器，此修正器於400V以上時利用雙相交錯操作，於400V以下時執行單相操作。實驗結果驗證，本文所提之架構於不同輸出電壓範圍內，其功率因數及輸入電流總諧波失真均可符合國際規範，且其最高轉換效率可達95.2%。

This thesis proposes a novel interleaved voltage-doubler boost converter and uses digital average current control to achieve power factor correction. The proposed converter uses a two-phase interleaved circuit to reduce the current stresses on components and electromagnetic interferences. Furthermore, a voltage-doubler circuit with two capacitors in series at the output terminal is cascaded to the two-phase interleaved circuit for high voltage applications. The capacitors of the voltage-doubler circuit are charged alternately by the two-phase interleaved operation; therefore, the voltage conversion gain of the proposed converter is two-times of a conventional boost converter. Besides, the proposed converter can also reduce the voltage stresses on power switches. The converter proposed in this thesis can be adjusted to the single-phase with the operation of a relay. Meanwhile, the voltage conversion gain is the same as a conventional boost converter. With the alteration between the two-phase interleaved and single-phase operations, a wider output voltage range that provides greater application elasticity can be realized. TI TMS320F28335 is used in this thesis to design and implement the proposed interleaved voltage-doubler boost converter for power factor correction with an AC input voltage of 110V, a DC output voltage between 200V to 700V and an output power of 700W. The proposed converter is activated in the two-phase interleaved operation and single-phase operation when the output voltage is larger than 400V and less than 400V, respectively. Experimental results indicate that the power factors and total harmonic distortion of input currents of the proposed converter at different output voltages can meet the international regulations. Besides, a maximum conversion efficiency of 95.2% can be achieved.

論文審定書 i
誌謝 ii
摘要 iii
Abstracti iv
目錄 v
圖目錄 vii
表目錄 x
第一章 緒論 1
1-1 研究背景 1
1-2 研究動機 3
1-3 論文大綱 4
第二章 功率因數修正與倍壓電路簡介 5
2-1功率因數與諧波失真定義 5
2-2功率因數修正器操作模式與控制方法介紹 8
2-2-1功率因數修正器操作模式 8
2-2-2功率因數修正器控制方法 9
2-3升壓型功率因數修正器 12
2-3-1單相升壓型轉換器 12
2-3-2雙相交錯式升壓型轉換器 16
2-4倍壓升壓型功率因數修正器 17
第三章 交錯式倍壓升壓型轉換器之原理 20
3-1交錯式倍壓升壓型轉換器電路架構分析 20
3-1-1功率開關責任週期大於0.5之動作模式分析 23
3-1-2功率開關責任週期小於0.5之動作模式分析 26
3-2升壓型轉換器損失估算 32
第四章 電路設計與控制 36
4-1電路元件與參數設計 36
4-1-1電感元件選擇 36
4-1-2輸出二極體選擇 39
4-1-3輸出電容元件選擇 39
4-1-4功率開關元件選擇 41
4-1-5橋式整流元件選擇 41
4-2周邊電路設計 42
4-2-1功率開關驅動電路 42
4-2-2取樣電路 43
4-2-3 EMI濾波器 47
4-3控制晶片與程式設計 48
4-3-1 TMS320F28335數位訊號控制器與CCStudio簡介 49
4-3-2數位式平均電流控制法 51
第五章 電路實驗結果 55
5-1交錯式倍壓升壓型轉換器實測 55
5-2交錯式倍壓升壓型轉換器單相運作實測 67
5-3交錯式倍壓升壓型轉換器損失計算 74
第六章 結論與未來展望 79
6-1結論 79
6-2未來展望 80
參考文獻 81

[1] P. N. Enjeti, R. Martinez, “A high performance single phase AC to DC rectifier with input power factor correction,” in Proc. IEEE APEC, San Diego, CA, pp. 190-195, Mar. 1993.
[2] W. M. Lin, M. M. Hernando, A. Fernandez, J. Sebastian, P. J. Villegas, “A new topology for passive PFC circuit design to allow AC-to-DC converters to comply with the new version of IEC1000-3-2 regulations,” in Proc. IEEE PESC, Cairns, Qld, vol. 4, pp. 2050-2055, Jun. 2002.
[3] W. Su, H. Ming, “Research and simulation of active power factor correction,” in Proc. IEEE CECNET, XianNing, pp. 5156 - 5158, Apr. 2011.
[4] EPARC, “電力電子學綜論(第二版),” 全華圖書股份有限公司,中華民國100年六月
[5] Y. Geng, Y. Liu, J. Chen, P. Luo, “Analysis and design of a predictive CCM power factor correction converter,” in Proc. IEEE ICCCAS, Chengdu, vol. 2, pp. 398-401, Nov. 2013.
[6] Gandhi B, M. Ezhilmaran, “Achieving high input power factor for DCM boost PFC converters by controlling variable duty cycle,” in Proc. IEEE ICCPEIC, Chennai, pp. 18-20, Apr. 2013.
[7] S. P. Yang, S. J. Chen, C. M. Huang, “Small-signal modeling and controller design of BCM boost PFC converters,” in Proc. IEEE ICIEA, Singapore, pp. 1096-1101, Jul. 2012.
[8] A. Prodic, J. Chen, R. W. Erickson, D. Maksimovic, “Digitally controlled low-harmonic rectifier having fast dynamic responses,” in Proc. IEEE APEC, Dallas, TX, USA, vol. 1, pp. 476-482, Mar. 2002.
[9] A. Prodic, J. Chen, D. Maksimovic, R. W. Erickson, “Self-tuning digitally controlled low-harmonic rectifier having fast dynamic response,”IEEE Tran. Power Electronics, vol. 18, pp. 420-428, Jan. 2003.
[10] A. Pandey, B. Singh, D. P. Kothari, K. Al-Haddad, “An adaline based fast voltage controller for single-phase PFC converters,” in Proc. IEEE IECON, vol. 3, pp. 2666-2671, Nov. 2003.
[11] E. Figueres, J. M. Benavent, G. Garcera, M. Pascual, “Robust control of power-factor-correction rectifiers with fast dynamic response,” IEEE Tran. Industrial Electronics, vol. 52, pp. 66-76, Feb. 2005.
[12] G. Chu, C. K. Tse, S. C. Wong, S. C. Tan, “A unified approach for the derivation of robust control for boost PFC converters,” IEEE Tran. Power Electronics, vol. 24, pp. 2531-2544, Oct. 2009.
[13] E. Figueres, J. M. Benavent, G. Garcera, M. Pascual, “A control circuit with load-current injection for single-phase power-factor-correction rectifiers,” IEEE Tran. Industrial Electronics, vol. 54, pp. 1272-1281, Jun. 2007.
[14] C. A. Canesin, I. Barbi, “Analysis and design of constant-frequency peak-current-controlled high-power-factor boost rectifier with slope compensation,” in Proc. IEEE APEC, San Jose, CA, vol. 2, pp. 807-813, Mar. 1996.
[15] L. Rosseto, G. Spiazzi, P. Tenti, “Control techniques for power factor correction converters,” Proc. PEMC’94, 1994.
[16] J. C. Salmon, “Techniques for minimizing the input current distortion of the current-controlled single-phase boost rectifier,” in Proc. IEEE APEC, Boston, MA, pp. 368-375, Feb. 1992.
[17] P. N. Enjeti, R. Martinez, “A high performance single phase AC to DC rectifier with input power factor correction,” in Proc. IEEE APEC, San Diego, CA, pp. 190-195, Mar. 1993.
[18] G. Cao, H. J. Kim, “A novel critical-conduction-mode bridgeless interleaved boost PFC rectifier,” in Proc. IEEE IPEC, Hiroshima, pp. 2587-2592, May 2014.
[19] R. C. Castello, R. Grino, E. Fossas, “Resonant Control of a Single-Phase Full-Bridge Unity Power Factor Boost Rectifier,” in Proc. IEEE CCA, Singapore, pp. 599-604, Oct. 2007.
[20] B. A. Miwa, D. M. Otten, M. E. Schlecht, “High efficiency power factor correction using interleaving techniques,” in Proc. IEEE APEC, Boston, MA, pp. 557-568, Feb. 1992.
[21] L. Balogh, R. Redl, “Power-factor correction with interleaved boost converters in continuous-inductor-current mode,” in Proc. IEEE APEC, San Diego, CA, pp. 168-174, Mar. 1993.
[22] R. Giral, L. M. Salamero, S. Singer, “Interleaved converters operation based on CMC,” IEEE Tran. Power Electronics, vol. 14, pp. 643-652, Jul. 1999.
[23] P. W. Lee, Y. S. Lee, D. K. W. Cheng, X. C. Liu, “Steady-state analysis of an interleaved boost converter with coupled inductors,” IEEE Tran. Industrial Electronics, vol. 47, pp. 787-795, Aug. 2000.
[24] H. A. C. Braga, I. Barbi, “A unity power factor rectifier based on a two-cell boost converter using a new parallel-connection technique,” in Proc. IEEE PESC, Baveno, vol. 2, pp. 1620-1626, Jun. 1996.
[25] 蔡偉倫, “具高降升壓比之新型雙向全波整流電路,” 國立中山大學,中華民國104年8月
[26] Y. Jang, M. M. Jovanovic, “Interleaved boost converter with intrinsic voltage-doubler characteristic for universal-line PFC front end,” IEEE Tran. Power Electronics, vol. 22, pp. 1394-1401,Jul. 2007.
[27] G. Moschopoulos, Shumin Li, “A soft-switched AC-DC boost converter with power factor correction and reduced switch voltage stress,” in Proc. IEEE CCECE, vol. 1, pp. 375-378, May 2003.
[28] J. Yamamoto, O. Miyashita, T. Yoshida, “A voltage-sensorless PFC voltage doubler,” in Proc. IEEE EPEPEMC, Novi Sad, pp. DS3c.12-1 - DS3c.12-6, Sept. 2012.
[29] C. Y. Lu, H. C. Chen, W. C. Chen, C. Y. Li, “Current sensorless control for dual-boost half-bridge PFC converter,” in Proc. IEEE ECCE, Montreal, QC, pp. 669-675,Sept. 2015.
[30] A. S. Martins, G. C. Flores, A. T. Barden, “DC-DC and AC-DC voltage doubler boost converter for UPS applications,” in Proc. IEEE COBEP, Praiamar, pp. 601-606, Sept. 2011.
[31] J. C. Salmon, “Circuit topologies for single-phase voltage-doubler boost rectifiers,” in Proc. IEEE APEC, Boston, MA, pp. 549-556, Feb. 1992.
[32] D. Borgonovo, S. A. Mussa, “Single-phase boost PFC voltage-doubler self-controlled using FPGA,”in Proc. IEEE PESC, Rhodes, pp. 4457-4463, Jun. 2008.
[33] D. Maksimovic, R. Erickson, “Universal-input, high-power-factor, boost doubler rectifiers,” in Proc. IEEE APEC, Dallas, TX, vol. 1, pp. 459-465, Mar. 1995.
[34] F. Musavi, D. S. Gautam, W. Eberle, W. G. Dunford, “A simplified power loss calculation method for PFC boost topologies,” in Proc. IEEE ITEC, Detroit, MI, pp. 1-5, Jun. 2013.
[35] A.R. Sam, S. Franz, S. Ken, “PFC boost converter design guide,” Infineon, Feb. 2016.
[36] 符曉,朱洪順, “TMS320F2833X DSP應用開發與實踐,” 北京航空航天大學出版社