臺灣博碩士論文加值系統

隨著高速數位訊號的演進與電路密度逐年提高，封裝的技術以及繞線的設計有了更高的複雜度，衍生出了許多不可忽視的訊號完整性問題。目前業界的先進封裝技術將多個裸晶組合在一個封裝之內，裸晶之間的連結使用線寬約為2 ~ 4微米的極細線(Fine-line)，先行封裝成FOWLP (Fan-Out Wafer Level Package)架構，再透過FC bump(Flip Chip bump)與傳統線寬25微米之有機基板進行複合式封裝結構。然而當高速數位訊號傳遞於極細線路時，諸多不連續的阻抗特性已不如傳統封裝上可以輕易控制，且因繞線的間距太小所引發的串擾現象，以及極細銅線所產生的導體損耗皆已不能忽略。
本論文探討下一世代100Gbps網通傳輸速度之差分訊號線結構(Differential Signal)之特性與分析，透過特性阻抗、返回損耗(Return Loss)、植入損耗(Insertion Loss)、串擾(Crosstalk)、時域之眼圖(Eye Diagram)與抖動(Jittter)等系統性分析手法提出最佳化的設計準則，並針對極細線路、不連續接面(VIA, FC Bump, Anti-pad, BGA ball)與有機基板電路等各自不同的結構，討論其電氣特性影響。

The rapid development of high-speed digital circuits leads to high complexity of layout design and the accompanying signal integrity problems, and presents a very serious challenge in packaging technology. The state-of-the-art FOWLP (Fan-Out Wafer Level Package) packaging technology assembles 2 to 3 bare chips inside a package using extremely fine lines (2~4 um) linking the chips, the package is then connected to an organic substrate with FC bump or conventional 25 um line to form a hybrid package. However, when high-speed signals travel on the extremely fine line, the impedance characteristics becomes very difficult to control compared to conventional packaging technology. Further, the crosstalk resulting from the extremely close proximity among signal lines and the conductor loss of copper wires due to skin effect are no longer negligible. Moreover, the dielectric loss of the organic substrate and the roughness of the copper line surface all make the design of hybrid packaging even more challenging.
This thesis focuses on the characterization of next-generation 100Gbps differential signal line structures. Effects of factors such as characteristic impedance, line widths, line separations, and roughness of the organic substrate and copper wires on the performance of crosstalk, insertion loss, return loss, eye diagram and jitter are thoroughly investigated to present suggestions on guidelines of optimal designs.

論文審定書 i
致謝 ii
摘要 iii
Abstract iv
目錄 v
圖表目錄 vii
第一章 緒論 1
1.1 研究背景 1
1.2 研究目的與方法 3
1.3 論文大綱 4
第二章 封裝技術之演進與訊號完整性 5
2.1 封裝技術的演進 5
2.2 晶片的整合技術 8
2.3 2.5D IC和扇出型晶圓級封裝 11
2.4 高頻封裝線路之電氣特性 14
2.4.1 有損傳輸線與反射損耗 17
2.4.2 介質損耗與導體損耗 20
2.4.3 串擾效應與差分訊號線 23
第三章 扇出型晶圓級封裝線路之電氣特性 29
3.1 極細線路之傳輸線架構 29
3.1.1極細線路之單端傳輸線特性 29
3.1.2線極細線之差分訊號傳輸線特性 35
3.2扇出型晶圓級封裝之探討 38
3.2.1架構介紹與傳輸線特性之探討 38
3.2.2 FC bump不連續面 44
3.2.3 Anti-Pad不連續面 47
第四章 複合式晶圓級封裝之電氣特性 52
4.1 有機基板線路之探討 52
4.1.1架構介紹及傳輸線特性 52
4.1.2 BGA ball 61
4.2 複合式結構之傳輸線特性 63
4.3 眼圖結果 72
第五章 結論 79
文獻探討 80

[1]“信號完整性分析Signal Integrity:Simplified ,”電子工業出版社,2005.
[2]ResearchGate,SoC versus SiP versus SoB, https://www.researchgate.net/figure/237651390_fig1_Fig-2-SoC-versus-SiP-versus-SoB-13
[3]T.Braun,S.Voges,“Large area compression molding for Fan-out Panel Level Packing,” IEEE 65th Electronic Components and Technology Conference (ECTC), Pages:1077-1083,DOI:10.1109/ECTC.2015.
[4]R.Tuominen,A.Gowda, “Component embedding platform for thin profile SiP, POP and fan-out WLP,”IEEE 17th Electronics Packaging and Technology Conference (EPTC), Pages:1-6,DOI:10.1109/EPTC.2015.
[5]T.Braun,S.Voges,“Material and Process Trends for Moving From FOWLP to FOPLP,”IEEE 17th Electronics Packaging and Technology Conference (EPTC), Pages:1–6, DOI:10.1109/EPTC.2015.
[6]V.S.Rao, C.T.Chong,“Development of High Density Fan Out Wafer Level Package (HD FOWLP) With Multi-layer Fine Pitch RDL for Mobile Applications,” IEEE 66th Electronic Components and Technology Conference (ECTC), Pages:1522-1529,DOI:10.1109/ECTC.2016.203
[7]J.X.Jiang,C.Z.Tan,“ A Novel Modular Design and Modeling Methodology for High Speed High Density Die Package PCB Co-Simulation and Model Library Creation,” IEEE 66th Electronic Components and Technology Conference (ECTC), Pages: 2264-2269,DOI:10.1109/ECTC.2016.
[8]N.C.Chen,T.H.Hsieh,“A Novel System in Package with Fan-out WLP for High Speed SERDES Application,” IEEE 66th Electronic Components and Technology Conference (ECTC), Pages:1495-1501,DOI:10.1109/ECTC.2016.
[9]H.C.Kuo,F.C.Chu,“High impedance design and investigation using TDR for fine lines on high density organic substrate,” International Conference on Electronics Packaging (ICEP), Pages:278-281,DOI:10.23919/ICEP.2017.
[10]TEXAS INSTRUMENTS, SerDes demystified, https://e2e.ti.com/blogs_/b/analogwire/archive/2014/05/08/get-connected-serdes-demystified
[11]56+Gbps Serial Transmission Using Duobinary Signaling ,DesignCon 2015.
[12]Package-PCB Interface Discontinuity Optimization For 50Gb/s Serdes Applications ,DesignCon 2014.
[13]W.Beyene,Y.C.Hahm,“Design, Modeling, and Characterization of Passive Channels for Data Rates of 50 Gbps and Beyond,” IEEE 64th Electronic Components and Technology Conference (ECTC), Pages: 730-735, DOI: 10.1109/ECTC.2014.
[14]CoDesign for 1TB System Utilizing 28Gbps Transceivers in 20nm Technology, DesignCon 2015.
[15]拓墣產業研究院,高階封裝技術之發展與應用, http://www.topology.com.tw/DataContent/report/高階封裝技術之發展與應用/14251
[16]six.man.日誌, IC載板與PCB版的差別, http://wwwsixman.blogspot.tw/2012/08/iicpcb.html
[17]IEEE,The Chip Scale Package, http://www.globalspec.com/reference/65512/203279/chapter-4-the-chip-scale-package
[18]Adhesives Technology for Electronic Applications:Materials,Processing,Reliability, https://books.google.com.tw/books?id=ZZ5kEWU5aHoC&pg=PA17&lpg=PA17&dq=Rigid+substrate-based+CSP&source=bl&ots=_gvkdzIU8O&sig=GFhGsHYmxupu-893KwP9MLwnAzQ&hl=zh-TW&sa=X&ved=0ahUKEwixzLrQjaHTAhUJwbwKHQoZBZgQ6AEIQjAD#v=onepage&q=Rigid substrate-based CSP&f=false
[19]SlideShare,IC Packaging, https://www.slideshare.net/santoshnimbal/ic-packaging
[20]fonearena,Qualcomm Snapdragon 625 14nm Octa-Core Soc,435 and 425 with LTE announced, http://www.fonearena.com/blog/174463/qualcomm-snapdragon-625-14nm-octa-core-soc-435-and-425-with-lte-announced.html
[21]T.Fukushima,A.Noriki, “3-D Sidewall Interconnect Formation Climbing Over Self-Assembled KGDs for Large-Area Heterogeneous Integration,” IEEE Transactions on Electron Devices, Pages:2912-2918, DOI:10.1109 /TED. 2017.
[22]Research Profiles, Development of High Performance and Low Power Three-Dimensional (3D) Integrated Circuits, http://www.rpip.tohoku.ac.jp/seeds/profile/77/lang:en
[23]R.Zhang,Jeffery C.C.Lo,“Design and Fabrication of a Silicon Interposer With TSVs in Cavities for Three-Dimensional IC Packaging,” IEEE Transactions on Device and Materials Reliability, Pages:189-193,DOI:10.1109/TDMR.2012.
[24]Z.Li,H.Shi,“Development of an Optimized Power Delivery System for 3D IC Integration with TSV Silicon Interposer,” IEEE 62nd Electronic Components and Technology Conference, Pages:678-682,DOI:10.1109/ECTC.2012.
[25]Y.Guillou,A.M.Dutron,“3D IC products using TSV for mobile phone applications:An industrial perpective,” European Microelectronics and Packaging Conference, Pages:1-6,2009.
[26]新通訊雜誌2010年3月號109期,垂直堆疊優勢多 3D IC倒吃甘蔗, http://www.2cm.com.tw/coverstory_content.asp?sn=1002260022
[27]International Electrostatic Discharge Workshop,2.5D and 3D integration IEW 2015, https://iew2015.wordpress.com/track_2-5d-and-3d-integration/
[28]K.Cho,H.Lee,“SIGNAL AND POWER INTEGRITY DESIGN OF 2.5D HBM ON SI INTERPOSER,”Pan Pacific Microelectronics Symposium (Pan Pacific), Pages:1-5,DOI:10.1109/PanPacific.2016.
[29]壹讀,20160414 NVIDIA的Pascal顯卡特色解析GP100強在哪、
20170205這些主流封裝標準不可不知,
https://read01.com/jgPO5B.html 、 https://read01.com/gLeQGB.html
[30]半導體行業觀察,經過瘋狂的2016中國半導體業產業邁入新階段, https://kknews.cc/tech/485x98g.html
[31]壹讀, 2017年FOWLP封裝技術市場急速擴大,
https://read01.com/PDkOOg.html
科技新報, 蘋果A10處理器的製程很強但新增的兩個小核心藏在哪呢, http://technews.tw/2016/09/19/apple-a10-process/
[32]吳柏毅,“封裝基板極細線路之訊號完整性分析,”國立中山大學碩士論文,September 2015
[33]G.Kim,K.Gharibdoust,“A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces,” IEEE Transactions on Circuits and Systems II: Express Briefs, Pages: 1126 -1130,DOI:10.1109/TCSII.2016.
[34]網際星空電子站,S-parameter基礎篇, http://www.oldfriend.url.tw/SI_PI/s_parameter basic.htm
[35]C.L.Holloway, and E.F. Kueser,“Quasi- closed Form Expression for Conductor Loss of CPW Lines, ” IEEE Trans. Microwave Theory Tech., vol. 43, no.12, pp.2695-2701, 1995.
[36]網際星空電子站,Crosstalk,
http://www.oldfriend.url.tw/SI_PI/crosstalk.htm
[37]蔡政憲,“防護線對高速數位信號在板級的電磁干擾影響探討,”國立交通大學碩士論文,May 2009
[38]李沛榮,“差模傳輸對在高速印刷電路中電磁輻射之量測與分析,”國立中山大學碩士論文,June 2003
[39]H.C.Kuo,M.F.Jhong,“Electrical Performance Analysis of Fine Line on High Density Package Substrate, ” IEEE CPMT Symposium Japan (ICSJ), Pages: 179-182,DOI:10.1109/ICSJ.2015.
[40]張復勝,“多層板電源接地平面電磁干擾分析與利用接地連通柱抑制輻射雜訊之設計,” 國立台灣大學碩士論文,June,2009.
[41]唐紹祐,“三維積體電路中直通矽晶穿孔的特性分析與電源完整性的應用,”國立台灣大學碩士論文,June,2011.
[42]H.Lim,J.Yang, “ High-speed flip chip package Co-Design with Optimization of anti-padsize variations on metal plane layout, ” IEEE 20th Workshop on Signal and Power Integrity (SPI), Pages:1-4,DOI:10.1109/SaPIW.2016.
[43]鄭宏祥,“有機基板上的貫穿孔之電性特性分析與模型化,”國立中山大學碩士論文,July 2007
[44]林育誠,“利用IBIS模型鍵結有限時域差分法模擬及分析訊號品質和電磁輻射,”國立中山大學碩士論文,July 2003
[45]信號完整性分析基礎系列之十--串行數據測試中的抖動算法, https://read01.com/moe34P.html
[46]黃詩雅,“高速系統構裝最佳眼高之傳輸結構優化設計,”國立台灣大學碩士論文,August,2016