臺灣博碩士論文加值系統

近年來高速數位電路中差動傳輸還是無法完全取代單端傳輸，例如記憶體電路就是利用單端線路進行讀取與寫入資料的動作，由於時脈上升和操作電壓降低，對於信號完整性而言，串音干擾的問題日益嚴重。
本論文提出新型的T-stub結構，利用提高電容比值的方法，可以有效抑制遠端串音干擾，接著透過萃取等效電路模型，可以讓設計更為簡單。模擬等效電路分別在時域與頻域的響應，並且和全波模擬軟體比較分析。
新型的T-stub結構和其他方法相比，不但可以避免布局面積浪費，遠端串音的抑制效果會更好，也不需額外的成本。但殘斷結構會使訊號線阻抗降低，為了彌補此缺點，最後再設計地層槽孔和T-stub結構結合，除了可以調整阻抗匹配，同時可以減少T-stub的數目。跟傳統單端訊號線相比，遠端串音電壓可以降低超過80%，並且透過眼圖來觀察信號品質的確有所改善。最後量測結果與模擬也相吻合。

For the past few years, the single-ended transmission line is still not entirely replaced by differential transmission line in the high speed circuit. Double Data Rate (DDR) memory system, which is single-end, parallel signal bus used for reading and writing data. As the speed of clock continues to increase and the operating voltage decrease, crosstalk becomes a critical problem that could degrade Signal Integrity (SI) performance.
A new T-stub alternated microstrip line structure is proposed and it can eliminate far-end crosstalk (FEXT) by increasing the mutual capacitance and decreasing the difference between capacitance ratio and inductance ratio. In order to design the T-stub structure, parameters of equivalent circuit are extracted. The equivalent circuit is also simulated in frequency domain and time domain, and then compared to full-wave simulation.
In comparison to other methods, the T-stub structure not only improves the performance but also reduces the layout area, and furthermore it does not need extra cost. To solve the impedance matching problem, a ground slot is adopted in T-stub alternated microstrip line structure, which can compensate for the decreasing impedance and reduce the number of stubs. This work can reduce the peak of Vfext by more than 80% compared with original microstrip line. By observing the eye diagram, the signal quality is improved. Also, measurement results are in good agreement with simulation results.

目錄
論文審定書.........i
誌謝.........ii
摘要.........iii
Abstract.........iv
目錄.........v
圖次.........vii
表次.........x
第一章 緒論.........1
1.1 研究背景與動機.........1
1.2 文獻回顧.........2
1.3 論文架構.........4
第二章 串音干擾.........5
2.1 串音干擾的形成.........5
2.1.1 電容性串音.........5
2.1.2 電感性串音.........6
2.1.3 近端串音和遠端串音.........7
2.2 防護串音干擾的方法.........8
2.2.1 防護線.........8
2.2.2 蛇行線.........9
2.2.3 殘段結構.........11
2.2.4 解決方法之總結.........12
2.3 奇模態與偶模態之電路分析.........14
2.3.1 奇模態.........14
2.3.2 偶模態.........17
2.3.3 等效電路參數分析.........20
第三章 T-stub結構.........22
3.1 Stub結構分析.........22
3.1.1 Stub長度、間距與數目探討.........22
3.2 T-stub結構.........29
3.2.1 等效電路.........29
第四章 T-stub結構與地層槽孔.........37
4.1 地層槽孔.........37
4.1.1 阻抗匹配.........41
4.2 量測結果與分析.........42
4.3 眼圖分析.........46
4.4 近端串音電壓分析.........48
第五章 結論.........50
參考文獻.........51

[1]T. L. Wu, F. Buesink, and F. Canavero, “Overview of signal integrity and EMC design technologies on PCB: Fundamentals and latest progress,” IEEE Trans. Electromag. Compat., vol. 55, no. 4, pp. 624–638, Aug. 2013.
[2]J. Buckwalter, B. Analui, and A. Hajimiri, “Data-dependent jitter and crosstalk-induced bounded uncorrelated jitter in copper interconnects,” in IEEE Int. Microw. Symp. Dig., Jun. 2004, pp. 627–1630.
[3]F. Mbairi, W. Siebert, and H. Hesselbom, “High-frequency transmission lines crosstalk reduction using spacing rules,” IEEE Trans. Compon. Packag. Technol., vol. 31, no. 3, pp. 601–610, Sep. 2008.
[4]G. Shiue, Z. Zhang, C. Yeh, and C. Huang, “Analysis and reduction of coupling noise in coupled striplines with inserted guard trace with different trace spacings,” IEEE Trans. Compon, Packag. Manuf. Technol., vol. 3, no. 8, pp. 1372–1383, Aug. 2013.
[5]L. Zhi, W. Qiang, and S. Changsheng, “Application of guard traces with vias in the RF PCB layout,” in Proc. IEEE Int. Symp. Electromagn. Compat., May 2002, pp. 771–774.
[6]K. Lee, H. B. Lee, H. K. Jung, J. Y. Sim, and H. J. Park, “A serpentine guard trace to reduce the far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines,” IEEE Trans. Adv. Packag. , vol. 31, no. 4, pp. 809–817, Nov. 2008.
[7]K. Lee, H. K. Jung, H. J. Chi, H. J. Kwon, J.Y. Sim, and H. J. Park, “Serpentine microstrip lines with zero far-end crosstalk for parallel high-speed DRAM interfaces,” IEEE Trans. Adv. Packag., vol. 33, no. 3, pp. 552–558, May 2010.
[8]M. S. Zhang, H. Z. Tan,, " Accurate Delay Extraction of Serpentine Lines for Next-generation High-Density DRAMs", IEEE Trans. Compon. Packag. Manuf. Technol., vol. 5, no. 12, Dec. 2015.
[9]K. Lee, H. Jung, J. Sim, and H. Park, “Reduction of transient far-end crosstalk voltage and jitter in DIMM connectors for DRAM interface,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 1, pp. 15–17, Jan. 2009.
[10]S. Chhay, R. Kunze, Y. Chu, “Crosstalk mitigation in dense microstrip wiring using stubby lines,” IEEE 22nd conference on EPEPS, 2013.
[11]S. H. Hall, G. W. Hall, and J. A. McCall, High-Speed Digital System Design, New York: Wiley, 2000, pp. 42-57.
[12]Y. S. Sohn, J. C. Lee, and H. J. Park, “Empirical equations on electrical parameters of coupled microstrip lines for crosstalk estimation in printed circuit board,” IEEE Trans. Adv. Packag., vol. 24, no. 4, pp. 521–527, Nov. 2001.
[13]B. R. Huang, K. C. Chen and C. L. Wang, “Far-End crosstalk noise reduction using decoupling capacitor,” IEEE Trans. Electromagn. Compat., vol. 58, no. 3, pp. 836–846, Jun. 2016.
[14]M. Kazerooni, A. Cheldavi, and M. Kamarei, “Crosstalk and electromagnetic interference noise investigation for a coupled pair of microstrip lines with a break in ground structure,” Microw., Antennas Propag., vol. 4, Sep. 2010.
[15]J. F. Buckwalter, “Predicting microwave digital signal integrity,” IEEE Trans. Adv. Packag., vol. 32, no. 2, pp. 280–289, May 2009.