近幾年，三五族高銦含量的砷化銦鎵通道高電子遷移率電晶體(High Electron Mobility Transistors，HEMTs)在高速度及低耗能邏輯應用方面展現出極大潛力，本研究中成功製作高速與低功率應用之高效能砷化銦通道高電子遷移率電晶體，並運用了先進的製程技術大幅提升了砷化銦通道高電子遷移率電晶體元件邏輯特性。
　　本論文中利用銦含量百分之百的砷化銦作為通道層材料成長於晶格匹配的磷化銦基板，並運用了電極板技術、非合金歐姆接觸技術、二次閘極蝕刻以及白金閘極掘入技術成功的製作出九十奈米閘極線寬的砷化銦高電子遷移率電晶體，利用這些技術使元件展現優異的邏輯特性。此研究比較了在低操作偏壓下(VDS=0.5V)電極板結構與平面結構電晶體之間的電性差異。
　　發現透過了電極板製程步驟改善了元件的電場分佈，使元件展現出非常高的崩潰電壓8.3伏特和相當低的次臨界擺幅 64.1mV/decade，此外，其開關電流比值達到 2.4×104，以及非常小的汲極能障降低 44mV/V，由這個研究結果可以證實，電極板技術能大幅改善邏輯元件特性，因此極具潛力作為下個世代的高速邏輯電晶體應用。

In the recent years, high indium content InGaAs-based HEMTs have high potential for high-speed and low-power logic application. 90 nm gate length InAs-channel high electron mobility transistors (HEMTs) have then been fabricated with success and characterized for high-frequency and low-power logic applications. The logical performance of the InAs-channel HEMTs was improved by using advance techniques.
　　In this thesis, the indium content is used and one hundred percent of the InAs-channel were grown on lattice match In-P substrates. The 90 nm InAs HEMTs processed with field plate techniques, Ti/Pt/Au non-alloyed ohmic process, two-step recess and Pt gate sinking technologies for logic applications were fabricated. Depletion and Enhancement Mode InAs Channel HEMTs of the developed 90 nm InAs HEMTs with these advanced processes perform better than the traditional InAs HEMTs at low applied voltage, for example: better current saturation, lower output conductance (go), lower negative threshold-voltage (VT) , smaller subthreshold swing (SS). The excellent electronic performances indicate that the developed 90 nm InAs HEMTs are suitable for high-speed and low voltage applications.
　　In this thesis, the fabrication of 90 nm InAs-channel HEMTs using field plate was developed. We have demonstrated that the field plate technique can realign the electrical field distribution to improve device performance. The devices show great performance in low applied voltage (VDS=0.5 V). The drain induced barrier lowering (DIBL) is 44 mV/V, subthreshold swing (SS) is 64.1 mV/decade, ION/IOFF ratio achieved 2.4 × 104, and much higher breakdown voltage achieved 8.3 V. These results show that the field plate technologies substantially improve logic device performance. Therefore, it has great potential for high-speed and low-power logic application for the next generation.

Content
摘要..................................................iii
Abstract................................................v
誌 謝.................................................vii
Table Captions.........................................xv
Chapter 1 Introduction
1.1 Background..........................................1
1.2 Advantages of III-V FETs for Logical Application....3
1.3 Motivation..........................................8
1.4 Thesis Goals and Organization.......................8
Chapter 2
Overview of III-V High-Electron-Mobility Transistors...10
2.1 The theory of III-V Devices........................10
2.2 The Structure of III-V HEMTs.......................12
2.4 Simulation Electric Field of III-V High-Electron-Mobility 　　Transistors (HEMTs)......................16
2.5 Advance Field Plate Technique......................18
Chapter 3
Process Development of InAs-channel FP-HEMTs...........21
3.1 Mesa Isolation and Sidewall etching................23
3.2 Ohmic Contact formation............................24
3.3 Si3N4 Passivation (Hat mask).......................24
3.4 Two-step T-shape gate recess process...............25
3.5 Gate metal deposition and Pt-Gate sinking formation .......................................................26
3.6 Second layer of Si3N4 passivation and field plate..29
Chapter 4
Electronic Characteristics for InAs HEMTs..............32
4.1 DC Characteristics.................................33
4.2 Transmission Line Model (TLM)......................36
4.3 Breakdown characteristics..........................38
4.4 Scattering Parameters..............................38
4.5 HEMTs’ Figures of Merit for Digital Applications...41
4.6 Current-Gain Cutoff Frequency (fT) and Maximum Oscillation Frequency (fmax)...........................47
Chapter 5
Experimental Results and Discussions...................52
5.1 DC Characteristics.................................52
5.2 Characteristics Comparison of Field Plate Devices between Different VDS.................................57
5.3 RF performance.....................................60
Chapter 6
Conclusion.............................................65
Reference

[1] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalierous, A. Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-performance and low-power logic transistor applications,” IEEE Transcations On Nanotechnology, vol. 4, no. 2, Mar. 2005.
[2] M. T. Bohr, “Nanotechnology goals and challenges for electronic applications,” IEEE Transaction on Nanotechnology, vol. 1, no. 1, pp. 56-62, Mar. 2002.
[3] R. Chau, S. Datta, and A, Majumdar, “Opportunities and Challenges of III-V Nanoelectronics for Future High-Speed, Low-Power Logic Applications,” in Proc. IEEE CSIC Dig., pp. 17-20, 2005.
[4]　 R. Chau, B. Doyle, S. Datta, J. Kavalieros, and K. Zhang, “Integrated nanoelectronics for the future,” Nat. Mater., vol. 6, no. 11, pp. 810–812, Nov. 2007.
[5] D. J. Frank, “Power-constrained CMOS scaling limits,” IBM J. Res. Dev., vol. 46, no. 2.3, pp. 235–244, Mar. 2002.
[6]　“International Technology Roadmap for Semiconductors (ITRS). Available: http://public.itrs.net/.”
[7]　A. Rahman, J. Guo, S. Datta, and M. S. Lundstrom, “Theory of ballistic nanotransistors,” IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1853–1864, Sep. 2003
[8] D. A. Antoniadis, I. Åberg, C. Ni Chleirigh, O. M. Nayfeh, A. Khakifirooz, and J. L. Hoyt, “Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations,” IBM J. Res. Dev., vol. 50, no. 4.5, pp. 363–376, Jul. 2006.
[9] M. S. Lundstrom, “On the mobility versus drain current relation for a nanoscale MOSFET,” IEEE Electron Device Lett., vol. 22, no. 6, pp. 293–295, Jun. 2001.
[10] A. Khakifirooz and D. A. Antoniadis, “Transistor Performance Scaling: The Role of Virtual Source Velocity and Its Mobility Dependence,” in IEDM Tech. Dig., 2006, pp. 26.4.1–26.4.4.
[11] J. A. del Alamo, “Nanometre-scale electronics with III-V compound semiconductors,” Nature, vol. 479, no. 7373, pp. 317–323, Nov. 2011.
[12] S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka, and N. Sugiyama, “Carrier-Transport-Enhancement Channel CMOS for Improved Power Consumption and Performance,” IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 252-257, Jan. 2008.

[13] S. Takagi, T. Irisawa, T. Tezuka, T. Numata, S. Nakaharai, N. Hirashita, Y. Moriyama, K. Usuda, E. Toyoda, S. Dissanayake, M. Shichijo, R. Nakane, S. Sugahara, M. Takenaka, and N. Sugiyama, “Carrier-Transport-Enhancement Channel CMOS for Improved Power Consumption and Performance,” IEEE Trans. Electron Devices, vol. 55, no. 1, pp. 252-257, Jan. 2008.
[14] Chien-I Kuo, Heng-Tung Hsu, and Edward Yi Chang, “InAs Channel-based Quantum Well Transistors for High-Speed and Low-Voltage Digital Applications,” Electrochemical and Solid-State Letter, 11(7), H193-H196, 2008.
[15] S. Oktyabrsky and P. Ye, Eds., Fundamentals of III-V Semiconductor MOSFETs. New York: Springer, 2010.
[16] J. A. del Alamo, “Nanometre-scale electronics with III-V compound semiconductors,” Nature, vol. 479, no. 7373, pp. 317–323, Nov. 2011.
[17] D.-H. Kim and J. A. del Alamo, “Logic Performance of 40 nm InAs HEMTs,” in IEDM Tech. Dig., 2007, pp. 629–632.
[18] N. Waldron, D.-H. Kim, and J. A. del Alamo, “90 nm Self-aligned Enhancement-mode InGaAs HEMT for Logic Applications,” in IEDM Tech. Dig., 2007, pp. 633–636.
[19] T.-W. Kim, D.-H. Kim, and J. A. del Alamo, “30 nm In0.7Ga0.3As Inverted-Type HEMTs with reduced gate leakage current for logic applications,” in IEDM Tech. Dig., 2009, pp. 483–486.
[20] T.-W. Kim, D.-H. Kim, and J. A. del Alamo, “60 nm self-aligned-gate InGaAs HEMTs with record high-frequency characteristics,” in IEDM Tech. Dig., 2010, pp. 30.7.1–30.7.4.
[21] D.-H. Kim, B. Brar, and J. A. del Alamo, “fT = 688 GHz and fmax = 800 GHz in Lg=40nm In0.7Ga0.3As MHEMTs with gm_max=2.7 mS/um,” in IEDM Tech. Dig., 2011, pp. 13.6.1–13.6.4.
[22] T. Mimura, S. Hiyamizu, T. Fujii, and K. Nanbu, “A New Field-Effect Transistor with Selectively Doped GaAs/n-AlGaAs Heterojunctions,” Jpn. J. Appl. Phys., vol. 19, pp. L225-L227, 1980.
[23] S.M. Sze, “High Speed Semiconductor Device,” Murryay Hill, New Jersey.
[24] T. Enoki, K. Arai, A. Kohzen and Y. Ishii, “InGaAs/InP double channel HEMT on InP,” Proc. 4th IPRM Conf., pp. 14-17, 1992.
[25] T. Akazaki, K. Arai, T. Enoki, and Y. Ishii, “Improved InAlAs/InGaAs HEMT Characteristics by Inserting an InAs layer into the InGaAs Channel,” IEEE Electron Device Lett., vol. 13, pp.325,1992.
[26] G. Meneghesso, D. Buttari, E. Perin, C Canali, and E. Zanoni, “Improvement of DC, low frequency and reliability properties of InAlAs-InGaAs InP-based HEMTs by means of InP etch stop layer,” in IEDM Tech. Dig., pp.227-230 1998.
[27] T. Suemitsu, H. Yokoyama, T. Ishii, T. Enoki, G. Meneghesso, and E. Zanoni, “30-nm two step-recess gate InP-based InAlAs/InGaAs HEMTs” IEEE Trans. Electron Devices, Vol. 49, no. 10, pp.1694-1700, Oct. 2002.
[28] Tanaka, Junko, et al. "Simulation of sub-0.1-mu m MOSFETs with completely suppressed short-channel effect." Electron Device Letters, IEEE 14.8 (1993): 396-399.
[29] Haddock, Joshua N., et al. "A comprehensive study of short channel effects in organic field-effect transistors." Organic electronics 7.1 (2006): 45-54.
[30] S. H. ., et al. "Comparison of short-channel effect and offstate leakage in symmetric vs. asymmetric double gate MOSFETs." SOI Conference, 2000 IEEE International. IEEE, 2000.
[31] Ferain, Isabelle, Cynthia A. Colinge, and Jean-Pierre Colinge. "Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors." Nature 479.7373 (2011): 310-316.
[32] Kunikiyo, Tatsuya, et al. "Reverse short-channel effect due to lateral diffusion of point-defect induced by source/drain ion implantation." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 13.4 (1994): 507-514.
[33] Chang, Chian-Sern, Ding-Yuan S. Day, and Simon Chan. "An analytical two-dimensional simulation for the GaAs MESFET drain-induced barrier lowering: a short-channel effect." Electron Devices, IEEE Transactions on 37.5 (1990): 1182-1186.
[34] Sun, Haifeng, et al. "Theoretical study of short channel effect in highly scaled GaN HEMTs." Radio-Frequency Integration Technology (RFIT), 2012 IEEE International Symposium on. IEEE, 2012
[35] Trew, R.J. Wide bandgap transistor amplifiers for improved performance microwave power and radar applications. 15th International Conference on Microwaves, Radar and Wireless Communications, MIKON - 2004, May 17-19 2004. 2004. Warszawa, Poland: Institute of Electrical and Electronics Engineers Inc., New York, NY 10016-5997, United States.
[36] Karmalkar, S. and U.K. Mishra, Enhancement of breakdown voltage in AlGaN/GaN high electron mobility transistors using a field plate. IEEE Transactions on Electron Devices, 2001. 48(8): p. 1515-1521.
[37] Johnson, F. Scott, et al. "Characterization of LPCVD of silicon nitride in a rapid thermal processor." MRS Proceedings. Vol. 146. Cambridge University Press, 1989.
[38] R. Williams, “Modern GaAs Processing Methods,” Artech House, Inc., 1991.
[39] T. Suemitsu, T. Enkoi, H. Yokoyama, Y. Ishii, “Improved recessed-gate structure for sub-0.1-um-Gate InP-based high electron mobility transistors,” Jpn. J. Appl. Phys., vol. 37, pp. 1365-1372, 1998.
[40] W. Liu, “Fundamentals of III-V Devices: HBTs, MESFETs, and HFETs/HEMTs,” John Wiley & Sons, Inc., 1999.
[41] D. H. Kim, J. A. Alamo, J. H. Lee, and K. S. Seo, “Performance Evaluation of 50 nm In0.7Ga0.3As HEMTs for beyond-CMOS logic applications,” in IEDM Tech. Dig., pp.767-770, 2005.
[42] L. H. Chu, E. Y. Chang, L. Chang, Y. H. Wu, S. H. Chen, H. T. Hsu, T. L. Lee, Y. C. Lien, and C. Y. Chang, “Effect of Gate Sinking on the Device Performance of the InGaP/AlGaAs/InGaAs Enhancement-Mode PHEMT,” IEEE Electron Device Lett., vol. 28, pp. 82-85, Feb. 2007.
[43] T. Akazaki, K. Arai, T. Enoki, and Y. Ishii, “Improved InAlAs/InGaAs HEMT Characteristics by Inserting an InAs Layer into the InGaAs Channel,” IEEE Electron Device Lett., vol. 13, pp. 325-327, Jun. 1992.
[44] G. F. Engen, and C.A. Hoer, “Thru-Reflect-Line:An Improved Technique for Calibrating the Dual Six-Port Automatic Network Analyzer,” IEEE Trans. On Microwave Theory and Techniques, vol. 27, no. 12, pp. 987-993, Dec. 1979.
[45] W. Liu, “Fundamentals of III-V Devices: HBTs, MESFETs, and HFETs/HEMTs,” John Wiley & Sons, Inc., pp. 293 1999.
[46] H. Philip Li, Olin L. Hartin, and Marcus. “An Updated Temperature-Dependent Breakdown Coupling Model Including Both Impact Ionization and Tunneling Mechanisms for AlGaAs/InGaAs HEMTs,” IEEE Transactions on Electron Devices, vol. 49, no. 9, Sep 2002.
[47] S. M. Sze. Physics of Semiconductor Devices, New York: Wiley, 3rd ed., with Kwok K. Ng, 2007, chapter 6.2.4, p. 315, ISBN 978-0-471-14323-9.
[48] Narain Arora (2007). Mosfet Modeling for VLSI Simulation: Theory And Practice. World Scientific. p. 210. ISBN 981-256-862-X
[49] Bohr, Mark T. "Interconnect scaling-the real limiter to high performance ULSI." International Electron Devices Meeting. INSTITUTE OF ELECTRICAL & ELECTRONIC ENGINEERS, INC (IEEE), 1995.
[50] Chau, Robert, et al. "Benchmarking nanotechnology for high-performance and low-power logic transistor applications."
Nanotechnology, IEEE Transactions on 4.2 (2005): 153-158.
[51] Liou JJ, Ortiz-Conde A, Garcia Sanchez FJ, Analysis and design of MOSFETs: modeling, simulation and parameter extraction, New York, USA: Kluwer Academic Publishers (1998).
[52] Liou JJ, Ortiz-Conde A, Garcia Sanchez FJ, Proceedings of IEEE HKEDM, pp. 31–8 (1997).
[53] Schroeder DK, Semiconductor material and device characterization, 2nd ed. New York: Wiley (1998).
[54] Oritiz-Conde A, Garcia Sanchez FJ, Liou JJ, Acta Cientifica Venezolana, pp. 176-87 (2000).
[55] R. Chau, S. Datta, and A. Majumdar, Proc. IEEE CSIC Dig., 17 (2005).
[56] Vivek Joshi, Kanak Agarwal, Dennis Sylvester, David Blaauw, IEEE, pp. 739-744 (2010).
[57] R. Chau, S. Datta, M. Docyz, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications”, IEEE Trans. Nanotechnology, Vol. 4, No. 2, pp. 153–158, 2005
[58] Dae-Hyun Kim et al., “Logic Suitability of 50-nm In0.7 Ga0.3As HEMTs for Beyond-CMOS Applications,” IEEE Trans. on electronic devices, pp. 2606-2613 (2007)
[59] S. H. Kim, et al., (Tokyo Uni.) VLSI2013, T50.
[60] S. W. Chang, et al., (TSMC) IEDM2013, p.417.
[61] T. W. Kim, et al., (Sematech) IEDM2013, p.425.
[62] C. –S. Shin, et al., (KANC, Sematch, GF) VLSI2014, p.30.
[63] C. –S. Shin, et al., (KANC, Sematch, GF) VLSI2014, p.31.
[64] Arun VT, et al., (Logic Tech.) VLSI2014, p.72.
[65] H. Wu, et al., (Purdue Uni.) VLSI2014, p.82.
[66] X. Zhou, et al., (IMEC) VLSI2014, p.166.
[67] L. Dong, et al., (Purdue Uni.) VLSI2014, p.50.
[68] D-H Kim et al., IEDM (2006)
[69] D-H Kim et al., IEDM (2007)
[70] D-H Kim et al., IEEE Trans. Electron Device (2007)