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研究生:林敏嵩
研究生(外文):Min-Song Lin
論文名稱:應用於低耗能邏輯線路之場效電極板增強型砷化銦通道高電子遷移率電晶體之特性研究
論文名稱(外文):Study of Enhancement Mode InAs HEMTs with Field Plate Technologies for Low-Power Logic Application
指導教授:施宙聰施宙聰引用關係張翼張翼引用關係
指導教授(外文):Jow-Tsong ShyEdward Yi Chang
口試委員:許恒通孫台平
口試委員(外文):Heng-Tung HsuTai-Ping Sun
口試日期:2016-12-19
學位類別:碩士
校院名稱:國立清華大學
系所名稱:光電工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:105
語文別:英文
論文頁數:75
中文關鍵詞:砷化銦高電子遷移速率電晶體電極板技術鉑金屬掘入製程高耐壓低漏電流
外文關鍵詞:InAsHEMTField platePt sinkingHigh breakdown voltagelow off-state current
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  近幾年,三五族高銦含量的砷化銦鎵通道高電子遷移率電晶體(High Electron Mobility Transistors,HEMTs)在高速度及低耗能邏輯應用方面展現出極大潛力,本研究中成功製作高速與低功率應用之高效能砷化銦通道高電子遷移率電晶體,並運用了先進的製程技術大幅提升了砷化銦通道高電子遷移率電晶體元件邏輯特性。
  本論文中利用銦含量百分之百的砷化銦作為通道層材料成長於晶格匹配的磷化銦基板,並運用了電極板技術、非合金歐姆接觸技術、二次閘極蝕刻以及白金閘極掘入技術成功的製作出九十奈米閘極線寬的砷化銦高電子遷移率電晶體,利用這些技術使元件展現優異的邏輯特性。此研究比較了在低操作偏壓下(VDS=0.5V)電極板結構與平面結構電晶體之間的電性差異。
  發現透過了電極板製程步驟改善了元件的電場分佈,使元件展現出非常高的崩潰電壓8.3伏特和相當低的次臨界擺幅 64.1mV/decade,此外,其開關電流比值達到 2.4×104,以及非常小的汲極能障降低 44mV/V,由這個研究結果可以證實,電極板技術能大幅改善邏輯元件特性,因此極具潛力作為下個世代的高速邏輯電晶體應用。
In the recent years, high indium content InGaAs-based HEMTs have high potential for high-speed and low-power logic application. 90 nm gate length InAs-channel high electron mobility transistors (HEMTs) have then been fabricated with success and characterized for high-frequency and low-power logic applications. The logical performance of the InAs-channel HEMTs was improved by using advance techniques.
  In this thesis, the indium content is used and one hundred percent of the InAs-channel were grown on lattice match In-P substrates. The 90 nm InAs HEMTs processed with field plate techniques, Ti/Pt/Au non-alloyed ohmic process, two-step recess and Pt gate sinking technologies for logic applications were fabricated. Depletion and Enhancement Mode InAs Channel HEMTs of the developed 90 nm InAs HEMTs with these advanced processes perform better than the traditional InAs HEMTs at low applied voltage, for example: better current saturation, lower output conductance (go), lower negative threshold-voltage (VT) , smaller subthreshold swing (SS). The excellent electronic performances indicate that the developed 90 nm InAs HEMTs are suitable for high-speed and low voltage applications.
  In this thesis, the fabrication of 90 nm InAs-channel HEMTs using field plate was developed. We have demonstrated that the field plate technique can realign the electrical field distribution to improve device performance. The devices show great performance in low applied voltage (VDS=0.5 V). The drain induced barrier lowering (DIBL) is 44 mV/V, subthreshold swing (SS) is 64.1 mV/decade, ION/IOFF ratio achieved 2.4 × 104, and much higher breakdown voltage achieved 8.3 V. These results show that the field plate technologies substantially improve logic device performance. Therefore, it has great potential for high-speed and low-power logic application for the next generation.
Content
摘要..................................................iii
Abstract................................................v
誌 謝.................................................vii
Table Captions.........................................xv
Chapter 1 Introduction
1.1 Background..........................................1
1.2 Advantages of III-V FETs for Logical Application....3
1.3 Motivation..........................................8
1.4 Thesis Goals and Organization.......................8
Chapter 2
Overview of III-V High-Electron-Mobility Transistors...10
2.1 The theory of III-V Devices........................10
2.2 The Structure of III-V HEMTs.......................12
2.4 Simulation Electric Field of III-V High-Electron-Mobility   Transistors (HEMTs)......................16
2.5 Advance Field Plate Technique......................18
Chapter 3
Process Development of InAs-channel FP-HEMTs...........21
3.1 Mesa Isolation and Sidewall etching................23
3.2 Ohmic Contact formation............................24
3.3 Si3N4 Passivation (Hat mask).......................24
3.4 Two-step T-shape gate recess process...............25
3.5 Gate metal deposition and Pt-Gate sinking formation .......................................................26
3.6 Second layer of Si3N4 passivation and field plate..29
Chapter 4
Electronic Characteristics for InAs HEMTs..............32
4.1 DC Characteristics.................................33
4.2 Transmission Line Model (TLM)......................36
4.3 Breakdown characteristics..........................38
4.4 Scattering Parameters..............................38
4.5 HEMTs’ Figures of Merit for Digital Applications...41
4.6 Current-Gain Cutoff Frequency (fT) and Maximum Oscillation Frequency (fmax)...........................47
Chapter 5
Experimental Results and Discussions...................52
5.1 DC Characteristics.................................52
5.2 Characteristics Comparison of Field Plate Devices between Different VDS.................................57
5.3 RF performance.....................................60
Chapter 6
Conclusion.............................................65
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