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研究生:許哲維
研究生(外文):Hsu, Che-Wei
論文名稱:基於交易臆測技術的動態存取記憶體控制器之快速模擬模型
論文名稱(外文):A Fast Simulation Model of DRAM Controller Based on Transaction Speculation
指導教授:黃稚存
指導教授(外文):Huang, Chih-Tsun
口試委員:劉靖家陳中和
口試委員(外文):Liou, Jing-JiaChen, Chung-Ho
口試日期:2017-07-05
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:56
中文關鍵詞:電子系統層級記憶體模型交易臆測
外文關鍵詞:ESLDRAMMemorySpeculation
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記憶體階層在系統晶片中扮演資料存取的重要角色。同時,隨著記憶體速度和容量的上升,記憶體的能量消耗更佔系統中重要的一部分。另外,根據我們的實驗,記憶體在系統中更佔了高達37% 的時間。因此,利用快速的電子系統層級的記憶體模組進行系統探索變成重要的一部分。
在現有的技術中,DRAMSim2 是一個基於週期模擬的記憶體模組。其他也有很多基於事件模擬的記憶體模組,如:DRAMSys 被提出。在這篇論文中,我們將介紹這些模組的概念。
我們提出對於記憶體指令臆測,以及記憶體省略更新等等方法去加速記憶體模組。根據臆測多少指令,我們可以分成兩部分,事務層級的方法及指令層級的方法。事務層級的方法在突發長度長的狀況下會有較好的表現。我們利用包含亂數、業界實際的軟體軌跡、SPEC 2006 等等不同範例測試我們提出的方法。根據實驗結果,我們的模組對於 DRAMSim2 可以加快達到兩個數量級。
我們也將所提出的方法應用在業界平台上的記憶體模組上。該記憶體模組有支援介面擴張與優化並與 RTL有相當高的精確度。根據實驗結果,我們的技術可以加速該模組 6 倍。
最後,我們也在系統平台上進行性能評估。利用我們提出的模組,不僅減少記憶體模組模擬的時間,也可以增進系統整體模擬時間,最高可達 4.4倍。
Memory hierarchy has played a decisive role in the System-on-Chip (SoC) for providing necessary data bandwidth to maximize the system performance. In addition, memory subsystems with growing capacity and operating speed also account for a significant fraction of the energy consumption. However, our evaluation also shows that the simulation of memory sub-system can take up to 37% of the full-system simulation time. Therefore, an accurate and fast electronic system-level (ESL) model of DRAM controllers, has become vital to the design evaluation of the SoC.
Among many high-level DRAM models nowadays, DRAMSim2 is a well-known cycle-based model which has been validated against the RTL design. In this thesis, we present an improved simulation model of DRAM controller based on DRAMSim2. First of all, an event-based extension of DRAMSim2 is addressed with the discussion and comparison with other existing approaches.
To boost the simulation speed, the transaction speculation technique is proposed to minimizes cumbersome synchronization that dominates simulated time. Two variations has been implemented, i.e., the command-based and transaction-based approach. Comparing our timing model of two variations, while the command-based approach performs efficiently in general, the transaction-based approach is even superior in realistic cases with burst memory transactions. In addition, we also present the technique of the bank-state update skipping to reduce computation.
Several experiments have been performed. Random memory transactions with different injection intervals, memory traces of SPEC 2006 benchmarks, and realistic GPU, ENC, DEC applications have been evaluated, showing the speedups up to 368.6 × against DRAMSim2.
Our simulation model has also been integrated into an industrial SoC virtual platform and validated against its RTL implementation with the extended interface protocol and scheduling policies for the cycle accuracy. Finally, the experiment on the full-system ESL platform also shows that the proposed simulation model can improve the entire simulation time up to 4.4×, enabling the efficient full-system evaluation and optimization in the early design phase.
1 Introduction 1
1.1 Motivation 1
1.2 Contribution 1
1.3 Thesis Organization 2
2 Previous Works 3
2.1 Basic DRAM Concepts 3
2.1.1 DRAM Parameters 7
2.2 DRAMSim2: A Cycle Based DRAM Model 9
2.3 Event Based DRAM Model 13
2.4 The ESL SOC Platform 16
3 Proposed Simulation Model with the Transaction Speculation 18
3.1 Speculation 18
3.1.1 Device Model Simplifiation 18
3.1.2 Data Structure of Commands and The Model of Command Queue 19
3.1.3 Command-Based Approach 21
3.1.4 Transaction-Based Approach 24
3.2 Bank State Update Skipping 28
3.3 Other Techniques 31
4 System Integration 32
4.1 Industrial Memory Controller Model 32
4.2 Power Model 36
4.3 Performance Monitor Unit 38
5 Result of Experiment 42
5.1 DRAM Subsystem Improvement 42
5.2 System Improvement 50
6 Conclusion and Future Work 53
6.1 Conclusion 53
6.2 Future Work 54
6.2.1 Improvement on Simulation Speed 54
6.2.2 Synthesizable ESL Model 54
6.2.3 System Performance Improvement 54
[1] D. C. Black, J. Donovan, B. Bunton, and A. Keist, “SystemC: From the Ground Up,”
2009.
[2] J. Reineke, I. Liu, and H. D. Patel, “PRET DRAM controller bank privatization for
predictability and temporal isolation,” in Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2011 Proceedings of the 9th International Conference on, Oct.
2011.
[3] P. Rosenfeld, E. Cooper-Balis, and B. Jacob, “DRAMSim2: a cycle accurate memory
system simulator,” Computer Architecture Letters, vol. 10, no. 1, pp. 16–19, Jan 2011.
[4] H.-C. Chiang, M.-Y. Wang, and C.-W. Wu, “DRAM system simulation speed-up by
effctive-cycle selection,” in 2014 International Symposium on Computer, Consumer
and Control (IS3C), Taichung, Taiwan, Jun. 2014, pp. 1053–1056.
[5] M. Jung, C. Weis, and N. Wehn, “DRAMSys: A flxible DRAM subsystem design space
exploration framework,” JPSJ Transactions on System LSI Design Methodology, vol. 8,
pp. 63–74, 2015.
[6] A. Hansson, N. Agarwal, A. Kolli, T. Wenisch, and A. N. Udipi, “Simulating DRAM
controllers for future system architecture exploration,” in 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Monterey, California, Mar. 2014, pp. 201–210.
[7] J.-H. Huang, “An event-based DRAM simulation model,” Master’s thesis, National
Tsing-Hua University, October 2012.
[8] J.-Y. Lai, P.-Y. Chen, T.-S. Hsu, C.-T. Huang, and J.-J. Liou, “Design and analysis of a
many-core processor architecture for multimedia applications,” in Signal & Information
Processing Association Annual Summit and Conference (APSIPA ASC), December 2012.
[9] E. Salminen, C. Grecu, T. Hamalainen, and A. Ivanov, “Application modelling and
hardware description for network-on-chip benchmarking,” in IET Computers & Digital
Techniques, September 2009, pp. 539–550.
[10] L. Lehtonen, E. Salminen, and T. D. Hämäläinen, “Analysis of modeling styles on
network-on-chip simulation,” in NORCHIP, November 2010.
[11] A. S. Initiative, “Open core protocol specifiation release 3.0,” Oct 2013.
[12] “Openrisc 1000 arhitecture manual,” http://opencores.org/orlk/Main_Page, 2011.
[13] C.-C. Wu, “An ESL DRAM subsystem for design evaulation of system chips,” Master’s
thesis, National Tsing-Hua University, January 2016.
[14] T.-S. Hsu, C.-C. Wu, C.-W. Hsu, C.-T. Huang, J.-J. Liou, Y.-H. Chen, and J.-M.
Lu, “Design space exploration with a cycle-accurate SystemC/TLM DRAM controller
model,” in VLSI Design, Automation and Test (VLSI-DAT), 2017 International Symposium on, 2017.
[15] Y. Kim, , W. Yang, and O. Mutlu, “Ramulator: A fast and extensible DRAM simulator,” IEEE Computer Architecture Letters, vol. 15, no. 1, pp. 45–49, 2015.
[16] 1Gb (32M× 32) GDDR5 SGRAM, SK hynix, 11 2009, rev. 1.
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