臺灣博碩士論文加值系統

“類神經網路”，眾所週知的，它是時下最熱門的主題之一，而其中又以具有圍棋能力而出名的人工智慧AlphaGo系統為最佳的例子。此系統最精髓的概念便是利用“類神經網路”的學習能力使電腦具有學習的功能，並利用電腦的自我練習以及自我對弈的形式使電腦最終擁有與人類在圍棋領域上能夠對弈的能力。因此，如何將“類神經網路”製作成晶片硬體而能達到上述的功能，將會是一個非常令人期待去探索的問題。
當今“類神經網路”的主流依然是使用電腦來進行運算，但是，以目前人類的認知： “頭腦”仍是人類已知所有運算系統中運算能力的強者之一、且消耗能量極少的運作系統，故，若能藉由仿生硬體設計來實現將“類神經網路”變成晶片硬體，便有可能使其運算過程中所需消耗的能量減低，使更多使用“類神經網路”架構的硬體系統皆能克服以往的功耗問題，而在“類神經網路”系統規模增大的過程中不致於消耗大量的能量。
然而，在“類神經網路”的研究探討中，“能否讓系統具有雜訊?”乃是最需要考量的。因為在“類神經網路”的架構中，若能將訊號加入雜訊，會使整體系統不致產生過度學習的狀況，因此，在硬體實現上會考慮加入類似產生高斯分佈雜訊的系統區塊。但由於此種系統區塊的設計將會使晶片的設計難度及系統功耗都會增加，所以，是否能利用晶片中電晶體本身的雜訊來使電路訊號加入雜訊而取代系統區塊的額外設計，便成為一個相當具有挑戰性、且令人躍躍欲試的目標了。
本論文的重點是：研究一種具有可調節雜訊能力的電晶體，且此電晶體元件適合於融入一般電路設計當中，可於既有的CMOS標準製程中予以完成，而不需要額外使用其他特殊的製程。因此，本論文將提出一個有效演算法來建立此電晶體的模擬模型，以及使用一個電路架構來嘗試使此電晶體的雜訊可控能力能在電路中加以實現，以期此電晶體能夠應用於“類神經網路”的硬體實現。

As everyone knows, the Neural Network is one of the most popular subject matters at the present days. The well known example is AlphaGo system which has the ability of artificial intelligence to play Chinese Chess (Wei Chi). The essence concept of AlphaGo system is to build up computer to have the self-learning function through the learning system of Neural Network. Furthermore, the final goal of Neural Network is to make the computer has the ability to play Wei Chi with human beings by using computer’s self-practice and self-playing. Therefore, how to produce the Neural Network into hardware of IC Chip for reaching the functions which are mentioned above becomes a very excited and expectable research theme.
Currently, the main trend of Neural Network is still using computer to do the operation, and for human beings’ understanding of today, “Being’s brain” is one of the strongest operation system, and is the operation system of depletion the least energy and capacity. Therefore, if we can create the design of Bionic Hardware to transfer the Neural Network into a hardware of IC chip, then we can reduce the energy and capacity depletion during doing the operations, besides, we can apply the good result either to the other hardware systems which are using the architectures of Neural Network or to the system expansion of Neural Network.
However, when we are researching the system of Neural Network, we have to point out one very important issue: “Whether we can add the noise into the system or not?” The reason is in the architecture of Neural Network, if we add the noise into system’s signal, we can prevent the whole system from the condition of over-studying. Therefore, when we try to create the hardware of IC chip, we have to consider about adding the System Block for producing the noise which is similar with the Gaussian Distribution Noise. No doubt, to design the System Block must increase the design hardness of IC chip and the depletion of energy and capacity. Based on these considerations, instead of doing extra design of System Block, how to use the noise which is from Transistor of IC chip to add it into Circuit’s signal becomes a very challenging and eager research goal.
The main point of this theme is to make a research of creating a transistor which has the function of noise adjustable. And the components of the transistor can be embedded into the design of general circuit. Besides, the transistor also can be completed the production by the standard process of CMOS stead of completing it by doing extra special process. Therefore, in the theme, I tried to propose an effective calculation method to build up the simulation model of transistor, to use the architecture of circuit for the purpose of conducting the function of noise controllable in the circuit, and to expect the fact can come true that the transistor can be applied to the hardware of IC chip of Neural Network.

致謝 i
摘要 ii
Abstract iii
目錄 v
圖目錄 vii
表目錄 xi
第一章 緒論 1
1.1 研究背景 1
1.2 研究貢獻 1
1.3 章節概述 2
第二章 文獻回顧 3
2.1 類神經網路 3
2.2 仿神經電路基本架構 5
2.3 雜訊可控電晶體元件 7
2.4 LDMOS功率電晶體元件設計、特性分析及其模型之建立 9
2.5 模型目標討論 12
第三章 雜訊可控電晶體之直流量測與模型探討 13
3.1 0.18um製程技術下雜訊可控電晶體之量測資料 13
3.1.1 汲極延伸0.3um類型之雜訊可控電晶體量測資料 14
3.1.2 汲極延伸0.4um類型之雜訊可控電晶體量測資料 16
3.1.3 汲極延伸0.5um類型之雜訊可控電晶體量測資料 18
3.2 模型預測 19
3.2.1 PMOS應用架構模型 20
3.2.2 固定電阻模型 21
3.2.3 操作原理探討與可變電阻模型架構設計 22
3.2.4 可變電阻模型 24
3.3 混合忽略式電流控制模型 26
3.3.1 電阻萃取分析 26
3.3.2 牛頓疊代法應用 29
第四章 雜訊可控電晶體之0.18um製程技術模型建立 32
4.1 模型建立 32
4.1.1 汲極延伸0.3微米類型之雜訊可控電晶體元件之模型建立 32
4.1.2 汲極延伸0.4微米類型之雜訊可控電晶體元件之模型建立 36
4.1.3 汲極延伸0.5微米類型之雜訊可控電晶體元件之模型建立 39
4.1.4 整合不同汲極延伸類型之雜訊可控電晶體元件之模型建立 43
4.2 模型驗證 50
4.2.1 汲極延伸0.3微米類型之雜訊可控電晶體元件之模擬驗證 51
4.2.2 汲極延伸0.4微米類型之雜訊可控電晶體元件之模擬驗證 52
4.2.3 汲極延伸0.5微米類型之雜訊可控電晶體元件之模擬驗證 54
第五章 雜訊可控電晶體之0.18um製程技術應用電路及驗證 56
5.1. 疊接反向器電路架構 56
5.2. 使用標準元件之疊接反向器電路量測與模擬 58
5.3. 使用標準元件之電路量測結果修正Native NMOS之模型 60
5.4. 用修正模型模擬驗證替換雜訊可控電晶體之疊接反向器電路 62
5.5. 驗證疊接反向器電路之雜訊控制能力 66
第六章 結論與未來展望 72
6.1 結論 72
6.2 未來研究方向 73
參考文獻 74

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