臺灣博碩士論文加值系統

本論文提出一個使用自適性時間比較器達到雜訊最佳化之低壓高能源效率十二位元連續近似(SAR)類比數位轉換器(ADC)。
為達到良好功率消耗表現，本論文所提出之類比數位轉換器操作於低電壓的 0.5伏特。提出的自適性時間比較器可以隨著不同的輸入訊號調整比較器的雜訊大小，處理較大的輸入訊號時，將比較器的雜訊調大，消耗較少的能源，當輸入訊號較小時，消耗較多的能源壓低比較器的雜訊，提高12位元類比數位轉換器的能源效率。
為驗證本電路，此架構使用90奈米1P9M互補式金氧半導體製程製作，核心電路面積為156.96×693.96μm2，在0.5伏特電源電壓及相對應的100千赫茲取樣頻率操作下，此晶片在Nyquist頻率訊號輸入時實現之SNDR為為66.26dB，其對應的ENOB為10.71 bit，功率消耗為0.81微瓦，等效的figure of merit (FoM)為4.82fJ/conversion-step。

This thesis presents a 0.5V 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) using adaptive time-domain comparator with noise optimization.
The proposed ADC operates at low supply voltage 0.5V to save power consumption. The proposed adaptive time-domain comparator can adjust comparator noise performance with input value. While input signal is large, the input-referred noise of comparator decreases and the power consumption increases. While input signal is small, the input-referred noise of comparator increases and power consumption decreases, which can save more power during 12bit conversion.
The prototype was fabricated in 90nm 1P9M CMOS technology with a core area of 156.96×693.63μm2. At 0.5V supply voltage and 100kS/s sampling rate, the ADC achieves SNDR from 66.26dB corresponding ENOB from 10.71bit at Nyquist-frequency input and consumes 0.81μW power, resulting in a figure of merit (FoM) from 4.82 fJ/conversion-step.

Abstract ii
Content iii
List of Figures vi
List of Tables ix
Chapter 1 Introduction 1
1.1 Architecture Selection 1
1.2 Performance Metrics of SAR ADC 3
1.2.1 Nyquist Criterion 3
1.2.2 Resolution 4
1.2.3 Quantization Error 4
1.2.4 Offset and Gain Error 5
1.2.5 Differential Nonlinearity 6
1.2.6 Integral Nonlinearity 6
1.2.7 Signal-to-Noise Ratio 7
1.2.8 Signal-to-Noise and Distortion Ratio 8
1.2.9 Effective number of bits 8
1.2.10 Figure of Merit 8
1.3 Target Specifications 8
1.4 Thesis Organization 10
Chapter 2 Successive Approximation Register ADC Overview 11
2.1 Introduction 11
2.2 Operation Procedure of Conventional SAR ADC 12
2.3 Considerations of Sample and Hold 13
2.3.1 On-Resistance of MOS Switch 14
2.3.2 Charge Injection 15
2.3.3 Clock feedthrough 16
2.3.4 KTC Noise 16
2.4 Considerations of Capacitive DAC 17
2.4.1 DAC Parasitic Capacitance 18
2.4.2 DAC Capacitor Mismatch 19
2.4.3 Settling Time 20
2.5 Considerations of Comparator 21
2.5.1 Input Offset 22
2.5.2 Kickback Noise 22
2.6 SAR Control Logic 23
2.7 Consideration of Voltage-to-Time Converter 25
2.7.1 Voltage-Controlled delay line (VCDL) 25
2.7.2 Conversion Gain 26
2.7.3 Noise 27
2.8 Summary 28
Chapter 3 Circuit Design Considerations 30
3.1 Differential SAR ADC 30
3.2 Sample and Hold 31
3.3 CDAC Switching Energy 32
3.4 Proposed Voltage-to-Time Converter 35
3.4.1 VCDL 36
3.4.2 Phase Detector (PD) 37
3.5 Digital SAR Control Logic 38
3.6 Summary 38
Chapter 4 Circuit Implementation of Successive Approximation ADC 39
4.1 Architecture of Proposed SAR ADC 39
4.2 Design of Voltage-to-Time Comparator 40
4.2.1 Design of VCDL 41
4.2.2 Design of Window Control 44
4.2.3 Design of Phase Detector 46
4.3 Design of Sample and Hold 48
4.4 Design of Capacitive DAC 49
4.5 Digital Control Logic 51
4.6 Pre-Layout and Post-Layout Simulations 54
4.7 Summary 56
Chapter 5 Measurement Results 57
5.1 Measurement Environment Setup 57
5.2 Chip Micrograph 58
5.3 Static Performance 58
5.4 Dynamic performance 59
5.5 Noise performance with different window 61
5.6 Performance Discussion 62
5.7 Performance Summary and Comparison 65
5.8 Summary 67
Chapter 6 Conclusion and Future Work 69
6.1 Conclusion 69
6.2 Future Work 69
Bibliography 71

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