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研究生:陳韋嶧
研究生(外文):Chen, Wei-Yi
論文名稱:晶片製程、電壓及溫度監測系統之建構及其數據分析
論文名稱(外文):Implementation of A Measurement System for PVT Monitoring of an IC and Its Data Analysis
指導教授:黃錫瑜黃錫瑜引用關係
指導教授(外文):Huang, Shi-Yu
口試委員:呂學坤李進福蒯定明周永發
口試委員(外文):Lu, Shyue-KungLi, Jin-FuKwai, Ding-MingChou, Yung-Fa
口試日期:2017-07-25
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:29
中文關鍵詞:監控系統製程、溫度、電壓晶片潛在性故障預測
外文關鍵詞:Monitoring SystemPVTpotential PVT-induced failure
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隨著積體電路技術的發展演進,可靠度變成越來越受大家所重視的議題,尤其是一些與人身安全相關的應用,例如車用電子設備,生物醫療晶片等等,為了保證在這些應用領域的晶片能在其生命週期中正常的運作,晶片的可靠度分析變得越來越重要。而我們已知晶片的可靠度又受到製程、電壓、溫度等因素影響。為了能檢查出晶片所受到製程、電壓、溫度效應的影響程度,在我們實驗室先前已提出一套具溫度效應補償的線上測試方法(Temperature-aware online test method)。而在這篇論文當中,我們以FPGA為系統控制中心,建構了一套監測系統去測量埋入了我們設計的感測元件之測試電路量測晶片,之後透過使用之前所提出的溫度效應補償的線上測試方案,可以分析實際操作時晶片所受到的製程、電壓、溫度效應影響。有了這些量測所獲得的資訊後,我們便可以在晶片實際損壞之前,提前檢測出因製程、電壓、溫度效應而引發的潛在性故障,之後透過適應性電壓調節、線上修復或是手動更換零件等修補方式,希望可以縮短甚至是避免不必要的系統停機時間。我們將在這篇論文中使用此監測系統來展示埋入了我們所設計的監測電路的晶片所測量到的數據及其結果分析。並且將其應用延伸,透過我們所量測到的晶片狀況來評估此一測量系統之供應電壓源狀況,判斷是否有電源電量低下的問題。
Reliability of an IC, concerning if an IC can function reliably over its designated lifetime in the field, has become more and more important in today’s safety-critical applications (e.g., automobile electronics, biomedical electronics and so on). It is known that reliability can be affected by PVT effects, (Process, Voltage and Temperature). These effects vary at different physical locations where an IC is operated. In order to verify the affect by PVT effects of an IC, temperature-aware online test method have been proposed previously. In this thesis, we propose a measurement system for PVT monitoring of an IC, through actually measure an IC which we insert monitors in it, we analysis the PVT effects of an IC in the field. With the obtained information, a potential PVT-induced failure can be alarmed in advance before it actually strikes, and thereby pre-cautious actions (such as adaptive voltage scaling, online repair, or even manual replacement) can be taken in advance to shorten or even avoid unnecessary system down time. A measurement system containing a test chip with the built-in design-for-monitoring circuitry will be used to demonstrate measurement data.
Abstract..........................................i
摘要..............................................ii
致謝.............................................iii
Content..........................................iv
List of Figures..................................vi
List of Tables.................................viii
Chapter 1 Introduction............................1
1.1 Introduction..................................1
1.2 Thesis Organization...........................3
Chapter 2 Preliminaries...........................4
2.1 Ring-Oscillator Based Monitor.................4
2.2 Design-for-Monitoring for an IC...............6
2.3 Online Test Flow..............................7
2.4 ROCP Modeling.................................8
Chapter 3 Implement of Measurement System........10
3.1 Test Chip Design.............................10
3.2 Measurement System Architecture..............12
3.3 System Operating and Data Flow...............14
Chapter 4 Measurement Data Analysis..............15
4.1 Process Variation............................15
4.2 Temperature Tracking.........................17
4.3 VDD-drop Monitoring..........................20
4.4 Low-battery Detection........................24
Chapter 5 Conclusion.............................27
References.......................................28
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[2] S. Pant, D. Blaauw, V. Zolotov, S. Sundareswaran, and R. Panda, “Vectorless Analysis of Supply Noise Induced Delay Variation,” Proc. of International Conference on Computer-Aided Design (ICCAD), pp 184-191, 2003.
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[7] H.-C. Fu, S.-Y. Huang, D.-M. Kwai, and Y.-F. Chou, "Temperature-Aware Online Testing of Power-Delivery TSVs," Proc. of IEEE Int'l 3D System Integration Conf., TS10.3.1 - TS10.3.6, (Sept. 2015).
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[13] Y. Miura, Y. Sato, Y. Miyake, and S. Kajihara, "On-chip Temperature and Voltage measurement for Field Testing", Proc. of European Test Symp., pp. 28-31, 2012.
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[15] C.-W. Tzeng, S.-Y. Huang, P.-Y. Chao, and R.-T. Ding, "Parameterized All-Digital PLL Architecture and Its Compiler to Support Easy Process Migration," IEEE Trans. on VLSI Systems (TVLSI), Vol. 22, No. 3, pp. 621-630, March 2014.
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