臺灣博碩士論文加值系統

由於類比數位轉換器提供真實世界和虛擬數位系統的溝通介面，其在現代單晶片系統中扮演非常重要角色。近年來，隨著可攜式裝置和環境監測網路的成長，低功耗類比數位轉換器的需求也隨之增加。本篇論文提出三種連續近似式類比數位轉換器的設計，其可以操作在低電壓並達到好的能源效率。
本論文的第一部分提出一個十一位元兩步驟切換的連續近似式類比數位轉換器。此轉換器只需要六十四個單位電容，為了操作在低電壓和降低亞穩態，比較器使用電壓抬升技巧。此轉換器實作在一百八十奈米製程，在每秒五十萬次的取樣頻率、0.6伏特的電壓下消耗5.02微瓦，其有效位元數為9.45位元，換算的性能指標為14.34 fJ/conversion-step。
本論文的第二部分提出一個十位元合併和分開切換的連續近似式類比數位轉換器。跟傳統方法相比，此轉換器降低83%的數位類比轉換器能量消耗，由於採用新的兩倍拔靴取樣保持電路，使得操作在低電壓下還能維持好的線性度。測式晶片使用九十奈米製程，操作在0.3伏特的電壓、在每秒九萬次的取樣頻率下消耗35奈瓦，其奈奎斯特輸入的有效位元數為8.38位元，換算的性能指標為1.17 fJ/conversion-step。
本論文的第三部分提出一個十位元前兩位元猜測的連續近似式類比數位轉換器。跟傳統方法相比，此轉換器降低90%的數位類比轉換器能量消耗和改善差動非線性和積分非線性√3/2倍，藉由採用新的堆疊輸入對的比較器和在最低有效位使用多數決比較，比較器的功率可以被降低。此轉換器實現在九十奈米製程，操作在0.3伏特的電壓、在每秒十五萬次的取樣頻率下消耗67.3奈瓦，其奈奎斯特輸入的有效位元數和無雜散動態範圍分別為8.38位元和70.7分貝，換算的性能指標為0.97 fJ/conversion-step。

Analog to digital converter (ADC) plays an important role in the modern system on a chip (SoC) because it provides interfaces between the real world and the virtual digital systems. Recently, the demand on low power ADC has dramatically increased due to the growth of portable devices and environmental monitoring network. This dissertation presents three successive approximation register (SAR) ADCs with good power efficiency at low voltage.
The first part of this dissertation presents an 11-bit two-step switching SAR ADC. It only requires 64 unit capacitors and employs supply-boost technique of comparator to operate at low supply voltage and reduce meta-stability. The prototype, fabricated in 0.18 μm CMOS technology, consumes 5.02 μW at 500 kS/s from a 0.6 V supply and achieves an ENOB of 9.45 bits and a Walden's figure of merit (FoMW) of 14.34 fJ/conversion-step, respectively.
The second part presents a 10-bit merge-and-split (MS) SAR ADC, which reduces DAC switching energy by 83% compared with conventional one. To operate at low voltage with good linearity, a new double-bootstrapped sample and hold (S/H) circuit is proposed. The test chip fabricated in 90 nm CMOS. With a 0.3 V supply and a Nyquist input, it consumes 35 nW at 90 kS/s and achieves an ENOB of 8.38 bits and a FoMW of 1.17 fJ/ conversion-step.
The third part presents a 10-bit first 2-bit guess (F2G) SAR ADC, which reduces DAC switching energy by 90% and improves the DNL and INL by √3/2 compared with conventional one. By the proposed comparator with stacked input pair and majority-vote comparison at the conversions of LSBs, the comparator power is reduced. Implemented in 90 nm CMOS technology, the prototype consumes 67.3 nW at 150 kS/s from a 0.3 V supply and achieves an ENOB of 8.85 bits and an SFDR of 70.7 dB at Nyquist input, respectively. The resultant FoMW are 0.97 fJ/ conversion-step.

摘要 i
Abstract iii
Table of Contents v
List of Figures ix
List of Tables xiv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Dissertation Organization 3
Chapter 2 Fundamentals of Analog-to-Digital Converter (ADC) 4
2.1 Background Elements of ADC 4
2.1.1 Nyquist Theorem 4
2.1.2 Resolution 4
2.1.3 Quantization Error 5
2.2 Performance Metrics of ADC 6
2.2.1 Offset Error 6
2.2.2 Gain Error 7
2.2.3 Differential Nonlinearity 8
2.2.4 Integral Nonlinearity 8
2.2.5 Signal-to-Noise Ratio 9
2.2.6 Signal-to-Noise and Distortion Ratio 9
2.2.7 Spurious-Free Dynamic Range 10
2.2.8 Effective Number of Bits 10
2.2.9 Figure of Merit 10
Chapter 3 Overview of Successive Approximation Register ADC 11
3.1 Architecture of Conventional SAR ADC 11
3.2 Operation Procedure of Conventional SAR ADC 12
3.3 Sample and Hold Circuit 13
3.3.1 Charge Injection 14
3.3.2 Clock Feedthrough 15
3.3.3 Sampling Speed 15
3.3.4 kT/C Noise 17
3.4 Capacitive Digital-to-Analog Converter 18
3.4.1 Parasitic Capacitors of DAC 19
3.4.2 Capacitor Mismatch 19
3.4.3 Settling Time 20
3.5 Comparator 21
3.5.1 Input Offset 22
3.5.2 Kickback Noise 23
3.6 SAR Controller and Clock Generator 23
3.7 Summary 25
Chapter 4 A 0.05 mm2 0.6 V 500 kS/s 14.3 fJ/Conversion-step 11-bit Two-Step Switching SAR ADC for 3-Dimensional Stacked CMOS Imager 27
4.1 Introduction 27
4.2 Two-step Switching SAR ADC 30
4.3 Comparator with Supply-Boost 39
4.4 SAR Controller 41
4.5 Measurement Results 43
4.5.1 Static Performance 43
4.5.2 Dynamic Performance 44
4.5.3 Power Consumption and Comparisons 46
4.6 Conclusion 48
Chapter 5 A 0.3 V 10-bit 1.17 f SAR ADC with Merge and Split Switching in 90 nm CMOS 49
5.1 Introduction 49
5.2 Merge and Split Switching 52
5.3 Circuit Implementation 63
5.3.1 Double-Bootstrapped Sample and Hold 63
5.3.2 Dynamic Comparator with Stacked Input Pair 67
5.3.3 Capacitive DAC Network 68
5.3.4 SAR Controller with Asymmetric Logic 70
5.4 Measurement Results 71
5.4.1 Static Performance 72
5.4.2 Dynamic Performance 72
5.4.3 Power Consumption and Comparisons 73
5.5 Conclusion 75
Chapter 6 A 0.3 V 10-bit 0.97 f SAR ADC with First 2-bit Guess in 90 nm CMOS 76
6.1 Introduction 76
6.2 First 2-bit Guess 78
6.3 Circuit Implementation 90
6.3.1 Double-Bootstrapped Sample and Hold 90
6.3.2 Dynamic Comparator with Stacked Input Pair 91
6.3.3 Capacitive DAC Network 94
6.3.4 Virtual Vcm Generation 97
6.4 Measurement Results 98
6.4.1 Static Performance 99
6.4.2 Dynamic Performance 99
6.4.3 Power Consumption and Comparisons 100
6.5 Conclusion 102
Chapter 7 Optimization of Low Voltage Low Power Successive Approximation Register ADC 103
7.1 Sample and Hold Circuit 103
7.2 Capacitive Digital-to-Analog Converter 104
7.3 Comparator 104
7.4 SAR Controller and Clock Generator 105
7.5 Summary 106
Chapter 8 Conclusions and Future Work 107
8.1 Conclusions 107
8.2 Future Work 108
Bibliography 109
Publication List 116
Journals 116
Conferences 116

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