在本論文中，首先會介紹CMOS影像感測器的市場、應用與基本電路架構發展。接著進入我第一個晶片設計，一個低功耗高動態範圍的智慧型影像感測器。依序介紹其研究動機和目標應用，然後是此晶片重要的特色，接著是電路的架構與操作，然後講解晶片量測並給一個小結。其後講到我的第二個晶片設計，一個高速數位式時間延遲積分影像感測器，相同的會依序介紹應用背景，規格推導與時間延遲積分的概念，然後帶到電路的架構與操作，接著講解晶片量測並給小結。最後是本論文結論與未來發展。
我們設計了一個擁有多種操作模式的智慧型影像感測器，包含了邊緣擷取、多點追蹤和高動態範圍影像等模式，其目標為在物聯網應用中架設無線感測網路。我們設計的像素包含了一個可操作於0.5伏之脈衝寬度調變感測器，其功能兼顧高動態範圍光電反應與固定圖像雜訊壓抑。借由局部像素間回饋網路、像素內低功耗動態邏輯與事件驅動接力讀出之對應週邊，我們可以實現陣列平行化影像訊號處理。我們使用台積0.18微米金氧半導體影像感測器製程來設計，製作了一個64乘64陣列大小的原型晶片。在多點追蹤模式時，量測到的追縱速度為14.28kfps、追蹤誤差為0.36像素而最大追蹤點數為四點。在高動態範圍影像模式時，量測可達到96.7dB之動態範圍。
我們設計了一個512行高速線性掃描影像感測器，其使用了32級數位時間延遲積分操作。感測器的訊號處理架構由類比前端電路、類比數位轉換器和數位累積器所組合而成，其設計為了操作速度、晶片面積和功耗效率來最佳化。我們設計了一個8行共享的十位元連續漸進類比數位轉換器並使用資料預測切換技術，配合著11位元的數位累積器在32級時間延遲積分操作下可以達到15位元資料長度。此晶片在32級時間延遲積分操作下可以提升訊雜比14.84dB，我們使用台積0.11微米背照式金氧半導體影像感測器製程來設計此線性時間延遲積分感測器，其操作掃描時間為104μs、像素大小為7.5μm而功耗為153.2μW/column。相較於其他已提出的晶片成果，我們提出的影像感測器於系統最佳化考量上更有競爭力。

In this thesis, I first introduce the market, the applications and the fundamental circuit architecture development of CMOS image sensor (CIS). And then I present my first IC work: “a low-power high dynamic range smart CIS”, which includes the research motivations and target applications, the key features, circuit descriptions and the measurements with summary. Next I demonstrate my second IC work: “a high-speed digital time delay integration (TDI) CIS”, which includes background, specifications, TDI concept, circuit descriptions and the measurements with summary. At the end of this thesis, I conclude these two works and explain the future works.
A smart image sensor is designed with multiple operation modes including edge extraction (EE), multi-point tracking (MPT), and high-dynamic-range (HDR) imaging for wireless sensor nodes in internet-of-things (IoT) applications. The pixel consists of a 0.5 V operated pulse-width-modulation (PWM) sensor for achieving high dynamic range (HDR) response and low fixed pattern noise. Array-level image signal processing is implemented by using a local inter-pixel feedback network, in-pixel low power dynamic logics, and a corresponding peripheral with an event-driven hand-shaking readout. A prototype chip with a 64 × 64 CIS array is designed and fabricated in TSMC 0.18-μm CIS technology. In MPT mode, the measured tracking speed is 14.28 kfps with an error of 0.36 pixels and a tracking capability up to four-point. In HDR imaging mode, the achieved dynamic range is 96.7 dB.
A 512-column high-speed linear scan image sensor is designed with 32-stage digital time-delay-integration operation. A signal processing architecture consists of analog front end (AFE), analog-to-digital converters (ADC), and digital accumulators (DA) are designed with optimization of timing, area, and power efficiency. An 8-column-shared 10b SAR ADC with data prediction switching (DPS) technique and 11b DA are proposed to achieve a data depth of 15 bit after 32-stage TDI. The achieved signal-to-noise ratio (SNR) boost is 14.84dB after 32-stage TDI operation. The proposed linear TDI sensor is implemented in 0.11-μm TSMC backside illumination (BSI) CIS technology with a line time of 104μs, a pixel pitch of 7.5μm, and a power consumption of 153.2μW/column. Compare with the state-of-the-art designs, the proposed image sensors are more competitive in system optimization.

ABSTRACT II
CONTENTS IV
LIST OF FIGURES VII
LIST OF TABLES XI
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.2 Research Goals and Contribution 8
1.3 Thesis Organization 9
Chapter 2 Overview of Conventional CMOS Image Sensors 11
2.1 Introduction 11
2.2 CIS Pixel Structure 14
2.2.1 Passive Pixel Sensor (PPS) 15
2.2.2 3-Transistor Active Pixel Sensor (APS) 16
2.2.3 4-Transistor Active Pixel Sensor (APS) 18
2.3 Noise in CMOS Image Sensor 19
2.3.1 Random Noise 20
2.3.2 Fixed Pattern Noise 27
2.4 Readout Architectures and Schemes 28
2.4.1 Correlated Double Sampling (CDS) 29
2.4.2 Rolling Shutter 29
2.4.3 Global Shutter 30
2.5 Summary 31
Chapter 3 Advanced CIS Techniques 33
3.1 Pixel Technology 33
3.2 Circuit Technique (High Dynamic Range) 35
3.2.1 Logarithmic Sensor 35
3.2.2 Dual-exposure 36
3.2.3 Pulse Modulation (PM) 37
3.3 Image Processing Technique 38
3.4 Circuit Technique (High SNR) 40
3.5 Summary 41
Chapter 4 A Low-Power High Dynamic Range Smart Image Sensor with Array-Level Image Signal Processing 43
4.1 Introduction 43
4.2 Operation Modes and Principle 45
4.2.1 High Dynamic Range Image Mode 45
4.2.2 Edge Extraction Mode 53
4.2.3 Multipoint Tracking Mode 54
4.3 Proposed Smart Sensor Circuits 57
4.3.1 Smart Sensor Pixel Core 58
4.3.2 Event-Driven Peripherals 61
4.4 Measurement Results 63
4.5 Summary 72
Chapter 5 A High-Speed Digital TDI Linear CMOS Image Sensor with Data Prediction Switching Technique 75
5.1 Introduction 75
5.2 Architecture and Principle 76
5.2.1 Architecture 77
5.2.2 Data Prediction Switching Technique Principle 84
5.3 Proposed Digital TDI Circuits 91
5.3.1 7.5μm Pixel Core Layouts 94
5.3.2 Time-Interleaved CDS 95
5.4 Measurement Results 97
5.5 Summary 104
Chapter 6 Conclusions 105
6.1 Summary 105
6.2 Future Works 106
BIBLIOGRAPHY 108

[1] Krymski, N. Khaliullin, H. Rhodes, “A 2e- Noise 1.3 Megapixel CMOS Sensor,” in Proc. IEEE Workshop CCD and Advance Image Sensors, June 2003.
[2] S. Kawahito, “Signal Processing Architectures for Low-Noise High-Resolution CMOS Image Sensors,” in Proc. Custom Integrated Circuits Conference (CICC), pp.695-702, 2007.
[3] S. Kawahito, N. Kawai, “Column parallel signal processing techniques for Reducing Thermal and random telegraph noise in CMOS image sensors,” in Proc. Int. Image Sensor Workshop, Maine, June 2007.
[4] N. Kawai and S. Kawahito, “Effectiveness of a correlated multiple sampling differential average for reducing 1/f noise,” IEICE Electronics Express, vol.2, no.13, pp. 379-383, 2005.
[5] T. Iida, M.A. Mustafa, L. Zhou, K. Yasutomi, S. Itoh, S. Kawahito, “A Column Parallel Cyclic ADC with an Embedded Programmable Gain Amplifier for CMOS Image Sensors,” Extended Abstract of the 2010 International Conference on Solid State Devices and Materials, pp. 1152-1153, 2010.
[6] A. El Gamal and H. Eltoukhy, “CMOS image sensors,” IEEE Circuits Devices Mag., vol. 21, no. 3, pp. 6–20, May/Jun. 2005.
[7] IC Insights, Inc., “CMOS Image Sensors See Higher Growth from Greater Diversity of Uses,” [Online]. Available: http://www.icinsights.com/news/bulletins/CMOS-Image-Sensors-See-Higher-Growth-From-Greater-Diversity-Of-Uses/
[8] IERC, “The definition of Internet of Things,” [Online]. Available: http://iotresearch.wikispaces.com/IoT%E7%9A%84%E5%AE%9A%E7%BE%A9
[9] IEI Integration Corp., “The solution of Internet of Things,” [Online]. Available: http://www.ieiworld.com/2013_GITEX_IoT_Solution/index.html
[10] J. Gubbi, R. Buyya, S. Marusic, and M. Palaniswami, “Internet of Things (IoT): A vision, architectural elements, and future directions,” Future Generation Computer Systems, vol. 29, no. 7, pp. 1645–1660, Sep. 2013.
[11] D. Bol, J. De Vos, F. Botman, G. de Streel, S. Bernard, D. Flandre, and J. D. Legat, “Green SoCs for a sustainable Internet-of-Things,” 2013 IEEE Faible Tension Faible Consommation (FTFC), 2013.
[12] NSPO, “Space Programs FORMOSAT-5 Program Description,” [Online]. Available: http://www.nspo.narl.org.tw/en2016/projects/FORMOSAT-5/program-description.html
[13] Chin Yin, Chin-Fong Chiu, Chih-Cheng Hsieh. “A 0.5 V, 14.28-kframes/s, 96.7-dB Smart Image Sensor With Array-Level Image Signal Processing for IoT Applications,” IEEE Transactions on Electron Devices, vol. 63, no. 3, 1134–1140, Feb. 2016.
[14] J. Yoshida. (2008, May, 27), “OmniVison adopts backside illumination technology for CMOS imager. EE Times,” [Online]. Available: http://www.eetimes.com/document.asp?doc_id=1308993
[15] Sony, “Sony develops back-illuminated CMOS image sensor, realizing high picture quality, nealy twofold sensitivity and low noise,” [Online]. Available: http://www.sony.net/SonyInfo/News/Press/200806/08-069E/index.html
[16] M. H. White, D. R. Lampe, F. C. Blaha, and I. A. Mack, “Characterization of surface channel CCD image arrays at low light levels,” IEEE Journal of Solid-State Circuits, vol. 9, pp. 1-12, 1974.
[17] J. A. Leñero-Bardallo, J. Fernández-Berni, and Á. Rodríguez-Vázquez, “Review of ADCs for imaging,” in Proc. IS&T/SPIE Electronic Imaging, 2014, pp. 90220I-90220I-6.
[18] M.-S. Shin, J.-B. Kim, M.-K. Kim, Y.-R. Jo, and O.-K. Kwon, “A 1.92-megapixel CMOS image sensor with column-parallel low-power and area-efficient SA-ADCs,” IEEE Transactions on Electron Devices, vol. 59, pp. 1693-1700, 2012.
[19] Y. Chae, J. Cheon, S. Lim, M. Kwon, K. Yoo, W. Jung, D.-H. Lee, S.Ham, and G. Han, “A 2.1 M Pixels, 120 Frame/s CMOS image sensor with column-parallel ADC architecture,” IEEE Journal of Solid-State Circuits, vol. 46, pp. 236-247, 2011.
[20] T. Watabe, K. Kitamura, T. Sawamoto, T. Kosugi, T. Akahori, T. Iida, K. Isobe, T. Watanabe, H. Shimamoto, and H. Ohtake, “A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs,” in Proc. IEEE International Solid-State Circuits Conference, 2012, pp. 388-390.
[21] M. F. Snoeij, A. J. Theuwissen, K. A. Makinwa, and J. H. Huijsing, “Multiple-ramp column-parallel ADC architectures for CMOS image sensors,” IEEE Journal of Solid-State Circuits, vol. 42, pp. 2968-2977, 2007.
[22] K. Chen, M. Afghani, P. Danielsson, and C. Svensson, “PASIC: A processor-A/D converter-sensor integrated circuit,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 1705-1708, 1990.
[23] A. Dickinson, S. Mendis, D. Inglis, K. Azadet, and E. Fossum, “CMOS digital camera with parallel analog-to-digital conversion architecture,” in Proc. IEEE Workshop on Charge Coupled Devices and Advanced Image Sensors, 1995.
[24] D. X. Yang, B. Fowler, and A. El Gamal, “A Nyquist-rate pixel-level ADC for CMOS image sensors,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 348-356, 1999.
[25] B. Fowler, A. El Gamal, and D. X. Yang, “A CMOS area image sensor with pixel-level A/D conversion,” in Proc. IEEE International Solid-State Circuits Conference, 1994, pp. 226-227.
[26] D. X. Yang, B. Fowler, and A. El Gamal, “A 128× 128 pixel CMOS area image sensor with multiplexed pixel level A/D conversion,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), 1996, pp. 303-306.
[27] U. Ringh, C. Jansson, and K. C. Liddiard, “Readout concept employing a novel on-chip 16-bit ADC for smart IR focal plane arrays,” in Proc. Aerospace/Defense Sensing and Controls, 1996, pp. 99-110.
[28] P. Denyer, D. Renshaw, G. Wang, M. Lu, and S. Anderson, “On-chip CMOS sensors for VLSI imaging systems,” in Proc. VLSI-91, pp. 157–166, 1991.
[29] J. Ohta, “Smart CMOS Image Sensors and Applications,” Boca Raton, FL: CRC Press, 2008.
[30] B. Fowler, A. El Gamal, and H. Tian, “Analysis of temporal noise in CMOS photodiode active pixel sensor,” IEEE J. Solid-State Circuits, vol. 36, pp.92 -101, 2001
[31] Y. Endo, Y. Nitta, H. Kubo. T. Murao, K. Shimomura, M. Kimura. K. Watanabe and S. Komori. “4-mocron pixel CMOS image sensor with low image lag and high-temperature operability,” in Proc. SPIE, vol. 5017, pp.196-204, Santa Clara, CA, Jan. 2003.
[32] I. Inoue, N. Tanaka, H. Yamashita, T. Uamaguchi, H. Ishiwata and H. Ihara. “Low-leakage-current and low-operating-voltage buried photodiode for a CMOS imager,” IEEE Trans. Electron Devices, vol. 50, no 1, pp.43-47, Jan. 2003.
[33] S. F. Yeh, C. C. Hsieh, C. F. Chiu, and H. H. Tsai, “An Image Lag Free CMOS Image Sensor with Constant-Residue Reset,” in Proc. IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2011.
[34] Junichi Nakamura, “Image Sensors and Signal Processing for Digital Still Cameras,” Taylor & Francis, 2006.
[35] R. N. Hall, “Electron-hole recombination in germanium,” Physical Review Letters, vol. 87, no. 2, pp. 387, Jul. 1952.
[36] W. Shockley and W. T. Read, Jr., “Statistics of recombination of holes and electrons,” Physical Review Letters, vol. 87, no 5, pp. 835-842, Sep. 1952.
[37] J. Johnson, “Thermal Agitation of Electricity in Conductors,” Physical Review Letters, vol. 32, no. 1, pp. 97-109, Jul. 1928.
[38] H. Nyquist, “Thermal Agitation of Electric Charge in Conductors,” Physical Review Letters, vol. 32, no. 1, pp. 110-113, Jul. 1928.
[39] A. L. McWhorter, “1/f Noise and Related Surface Effects in Germanium,” PhD dissertation, Massachusetts Institute of Technology, 1955.
[40] Xinyang Wang, “Noise in Sub-Micron CMOS Image Sensors,” PhD dissertation, Delft Technology University, 2008.
[41] Yue Chen, “Low-Noise CMOS Image Sensors for Radio-Molecular Imaging,” PhD dissertation, Delft Technology University, 2012.
[42] Sungho Suh, “A Study on Low Noise Wide Dynamic Range CMOS Image Sensors Using Low Noise High Gain Readout Circuits,” Doctoral Thesis, Shizuoka University, 2010.
[43] I. Takayanagi etc. “A 600×600 Pixel, 500 fps CMOS Image Sensor with a 4.4μm Pinned Photodiode 5-Transistor Global Shutter Pixel,” in Proc. Int. Image Sensor Workshop, Ogunquit Maine, USA, 2007.
[44] Yang Liu “The Design of a High Dynamic Range CMOS Image Sensor in 110nm Technology,” Master thesis, Delft University of Technology, pp. 19-20, Aug. 2012.
[45] K. Yasutomi, S. Itoh, and S. Kawahito, “A Two-Stage Charge Transfer Active Pixel CMOS Image Sensor With Low-Noise Global Shuttering and a Dual-Shuttering Mode,” IEEE Trans. Electron Devices, vol. 58, pp. 740-747, 2011.
[46] S. G. Wuu, C. -C. Wang, B. C. Hseih, Y. L. Tu, C. H. Tseng, T. H. Hsu, R. S. Hsiao, S. Takahashi, R. J. Lin, C. S. Tsai, Y. P. Chao, K. Y. Chou, P. S. Chou, H. Y. Tu, F. L. Hsueh and L. Tran, “A leading-edge 0.9um pixel CMOS image sensor technology with backside illumination: Future challenges for pixel scaling,” IEEE IEDM Tech. Dig., 2010, pp. 14.1.1-14.1.4.
[47] H. Rhodes, D. Tai, Y. Qian, D. Mao, V. Venezia Wei Zheng, Z. Xiong, C. Y. Liu, K. C. Ku, S. Manabe, A. Shah, S. Sasidhar, P. Cizdziei, Z. Lin, A. Ercan, M. Bikumandla, R. Yang, P. Matagne, C. Yang, H. Yang, T. J. Dai, J. Li, S. G. Wuu, D. N. Yaung, C. C. Wang, J. C. Liu, C. S. Tsai, Y. L. Tu, T. H. Hsu, “The mass production of BSI CMOS image sensors,” in Proc. Int. Image Sensor Workshop, 2009.
[48] S. G. Chamberlain, J. P. Y. Lee, “A novel wide dynamic range silicon photodetector and linear imaging array,” IEEE Trans. Electron Devices, vol. ED-31, no. 2, pp. 175-182, Feb. 1984.
[49] S. Kavadias, B. Dierickx, D. Scheffer, A. Alaerts, D. Uwaerts, and J. Boagaerts, “A logarithmic response CMOS image sensor with on-chip calibration,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp.1146-1152, Aug. 2000.
[50] O. Yadid-Pecht and E. R. Fossum, “Wide intrascene dynamic range CMOS APS using dual sampling,” IEEE Trans. Electron Devices, vol. 44, no. 10, pp. 1721-1723, Oct. 1997.
[51] Y. Oike, A. Toda, T. Taura, A. Kato, H. Sato, M. Kasai, and T. Narabu, “A 121.8dB Dynamic Range CMOS Image Sensor using Pixel-Variation-Free Midpoint Potential Drive and Overlapping Multiple Exposures,” in Proc. Int. Image Sensor Workshop, Jun. 2007, pp. 30-33.
[52] K. Dongsoo, C. Youngcheol, C. Jihyun, and H. Gunhee, “A Dual-Capture Wide Dynamic Range CMOS Image Sensor Using Floating-Diffusion Capacitor,” IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2590-2594, Oct. 2008.
[53] K.P. Frohmader. “A novel MOS compatible light intensity-to-frequency converter suited for monolithic integration,” IEEE J. Solid-State Circuits, vol. 17, no. 3, pp.588–591, Jun. 1982.
[54] R. Muller. “I2/L timing circuit for the 1 ms-10 s range,” IEEE J. Solid-State Circuits, vol. 12, no. 2, pp.139–143, Apr. 1977.
[55] S. W. Smith, “The Scientist and Engineer's Guide to Digital Signal Processing,” [Online]. Available: http://www.dspguide.com/ch24/2.htm
[56] H.-S. Wong, Y. L. Yao, and E. S. Schlig, “TDI charge-coupled devices: Design and applications,” IBM J. Res. Develop., vol. 36, no. 1, pp. 83-105, Jan. 1992.
[57] J. F. Johnson, “Modeling imager deterministic and statistical modulation transfer functions,” Appl. Opt., vol. 32, no. 32, pp. 6503–6513, Nov. 1993.
[58] M. Zhang, A. Bermak, X. Li, and Z.Wang, “A low power CMOS image sensor design for wireless endoscopy capsule,” in Proc. IEEE Biomedical Circuits Syst. Conf., pp. 397–400, Nov. 2008.
[59] C.-L. Lee and C.-C.Hsieh, “A 0.8-V 4096-Pixel CMOS Sense-and -Stimulus Imager for Retinal Prosthesis,” IEEE Trans. Electron Devices, vol. 60, no. 3, pp. 1162–1168, Mar. 2013.
[60] S. Shishido, Y. Oguro, T. Noda, K. Sasagawa, T. Tokuda, and J. Ohta, “CMOS image sensor for recording of intrinsic-optical-signal of the brain,” in Proc. IEEE Int. Conf. SoC Design, pp. 190–193, Nov. 2009.
[61] M.-T. Chung, C.-L. Lee, C. Yin and C.-C.Hsieh, “A 0.5 V PWM CMOS Imager With 82 dB Dynamic Range and 0.055% Fixed-Pattern-Noise,” IEEE J. Solid-State Circuits, vol. 48, no. 10, pp. 2522–2530, Oct. 2013.
[62] T. G. Constandinou and C. Toumazou, “A Micropower Centroiding Vision Processor,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1430–1443, Jun. 2006.
[63] J. Choi, S. Park, J. Cho and E. Yoon, “A 3.4-μW Object-Adaptive CMOS Image Sensor With Embedded Feature Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging,” IEEE J. Solid-State Circuits, vol. 49, no. 1, pp. 289–300, Jan. 2014.
[64] M. Gottardi, N. Massari and S. A. Jawed, “A 100 μW 128 × 64 Pixels Contrast-Based Asynchronous Binary Vision Sensor for Sensor Networks Applications,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1582–1592, May. 2009.
[65] S. Chen, W. Tang, X. Zhang, and E. Culurciello, “A 64 × 64 pixels UWB wireless temporal-difference digital image sensor,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 12, pp. 2232–2240, Dec. 2012.
[66] T. S. Gotarredona and B. L. Barranco, “A 128 × 128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 827–838, Mar. 2013.
[67] C. Yin and C.-C. Hsieh, “A 1V 14kfps Smart CMOS Imager with Tracking and Edge-detection Modes for Biomedical Monitoring,” in Proc. IEEE Int. Symp. on VLSI-DAT, pp. 1–4, Apr. 2013.
[68] S.-H. Yang, Y. You and K.-R. Cho, “A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free,” IEICE Trans. Electron., vol. E86-C, no. 3, pp.496–505, Mar. 2003.
[69] S. Chen and A. Bermak, “Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 3, pp. 346–357, Mar. 2007.
[70] G. Lepage, D. Dantès, and W. Diels, “CMOS long linear array for space application,” in Proc. SPIE 6068, Sensors, Cameras, and Systems for Scientific/Industrial Applications VII, 606807, Feb. 2006.
[71] G. Lepage, J. Bogaerts, and G. Meynants, “Time-delay-integration architectures in CMOS image sensors,” IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2524–2533, Nov. 2009.
[72] J.-H. Chang, K.-W. Cheng, C.-C. Hsieh, W.-H. Chang, H.-H. Tsai, and C.-F. Chiu, “Linear CMOS image sensor with time-delay integration and interlaced super-resolution pixel,” in Proc. IEEE Sensors, 2012, pp. 1–4.
[73] K. Nie, S. Yao, J. Xu, J. Gao, and Y. Xia, “A 128-stage analog accumulator for CMOS TDI image sensor,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 61, no. 7, pp. 1952–1961, Jul. 2014.
[74] E. Bodenstorfer, J. Fürtler, J. Brodersen, K. J. Mayer, C. Eckel, K. Gravogl, and H. Nachtnebel, “High-speed line-scan camera with digital time delay integration,” in Proc. SPIE 6496, Real-Time Image Processing 2007, 64960I, Feb. 2007.
[75] K. Nie, R. J. Xu, and Z. Gao, “A 128-Stage CMOS TDI Image Sensor With On-Chip Digital Accumulator,” IEEE Sensors Journal, vol. 16, no. 5, pp. 1319–1324, Mar. 2016.
[76] H.-J. Kim, S.-I. Hwang, J.-W. Kwon, D.-H. Jin, B.-S. Choi, S.-G. Lee, J.-H. Park, J.-K. Shin, and S.-T. Ryu, “Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi- column-parallel SAR ADCs,” in Proc. IEEE A-SSCC, 2015, pp. 1–4.
[77] B. Murmann, “ADC Performance Survey 1997-2015,” [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html.
[78] J.-Y. Lin, K.-H. Chang, C.-C. Kao, S.-C. Lo, Y.-J. Chen, P.-C. Lee, C.-H. Chen, C. Yin, and C.-C. Hsieh, “An 8-bit column-shared SAR ADC for CMOS image sensor applications,” in Proc. IEEE ISCAS, 2015, pp. 301–304.
[79] E. R. Fossum, and D. B. Hondongwa, “A Review of the Pinned Photodiode for CCD and CMOS Image Sensors,” IEEE J. Electron Devices Society, vol. 2, no. 3, pp. 33–43, May 2014.