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研究生:黃子恆
研究生(外文):Huang, Tzu Heng
論文名稱:應用於邏輯核心速度分級之寬頻時脈訊號產生方法
論文名稱(外文):A Wide-Range Clock Signal Generation Scheme for Speed Grading of a Logic Core
指導教授:黃錫瑜黃錫瑜引用關係
指導教授(外文):Huang, Shi Yu
口試委員:蒯定明周永發趙家佐
口試日期:2017-01-13
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:39
中文關鍵詞:速度分級速度級距最快速度觸發後擷取鎖相迴路產生器時脈訊號產生
外文關鍵詞:speed gradingspeed binningmaximum speedlaunch-off-capturePLL compilerclock generation
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對於先進的多核心晶片系統,我們必須確認其運作效能保有足夠的剩餘量,以使其能容忍諸如製程、電壓供應、溫度等等的變異。因此,有必要對每一邏輯合新加入內建速度分級測試(Built-In Speed Grading, BISG)之功能,使用者方能確認晶片是否能處於正常運作狀態,同時亦能作為動態供應電壓調控之依據。基本上,邏輯核心之速度分級(Speed Grading)方法是藉由不斷重複一樣的測試步驟,藉由改變每次的測試時脈頻率來得到待測核心之最快運作速度,舉例來說,此測試步驟可為針對延遲測試採取觸發後擷取(launch-off capture, LoC)之內建自測(Built-In Self-Test, BIST)。在此篇論文中,我們提出了一個可合成的寬頻時脈訊號產生方法,並將之應用於一個易於使用的速度分級方法。此時脈訊號產生方法主要包含了使用可合成的全數位鎖相迴路(All-Digital Phase-Locked Loop, ADPLL)、計數型除頻器以及倍頻電路。在90奈米製程下,其產生的寬頻時脈訊號頻率範圍將可含蓋五千萬赫茲至二十億赫茲,因此其可支援各種有著不同供應電壓、運作速度等等面向的邏輯核心。同時,因此時脈訊號產生方法為全細胞架構,其可容易地進行製程轉移。
In a modern multi-core SoC, the Built-In Speed Grading (BISG) of each logic core is often necessary in order to ensure an adequate operating margin for accommodating all kinds of variations (e.g., PVT variation) and to guide the dynamic VDD tuning process as well. In general, a speed grading method for a logic core can be performed by repeating a specific delay test session (e.g., built-in self-test with the latch-off capture scheme), with varying test clock frequencies to derive the maximum operating speed of a specific core under test. In this thesis, we propose an easy-to-use speed grading method featuring a wide-range synthesizable clock generation scheme so that it can support a logic core that could be used with different supply voltages and speeds in different application domains. The clock generation scheme mainly uses the fully synthesizable cell-based phase-locked loop (PLL), the counter-based frequency divider, and the frequency doubling circuit. The generated wide-range clock signal can span from 50MHz to 2GHz under 90nm technology. Since the circuit is fully cell-based, it is easy to do process migration.
Abstract i
摘要 ii
Content iii
List of Figures iv
List of Tables vi
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 3
Chapter 2 Preliminaries 4
2.1 Generic Speed Grading Method 4
2.2 Related work 8
Chapter 3 Wide-Range Clock Signal Generation Scheme 10
3.1 Built-In Speed Grading Architecture 10
3.2 Specification of Generated Clock Signal 11
3.3 Proposed Clock Generation Scheme 13
3.4 Test Clock Signal Generation 24
3.5 Revisited Speed Grading Flow 25
Chapter 4 Experimental Results 27
4.1 Test Method Verification 27
4.2 Performance of Clock Generation 29
Chapter 5 Conclusion 33
References 34
Appendix 37
[1] X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, and N. Tamarapalli, “High-Frequency, At-Speed Scan Testing,” IEEE Design Test Computers, Vol. 20, No. 5, pp. 17–25, Sep.–Oct. 2003.
[2] H. Yan and A. D. Singh, “Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Result from Neighboring die,” Proc. Int'l Test Conf., pp. 105-111, 2003.
[3] J. Lee and E. J. McCluskey, “Failing Frequency Signature Analysis,” Proc. Int'l Test Conf., pp. 1-8, 2008.
[4] H.-J. Hsu, C.-C. Tu, and S.-Y. Huang, “Built-In Speed Grading with a Process-Tolerant ADPLL,” Proc. Asian Test Symp., pp. 384–389, 2007.
[5] A. Chandra, “Hot Topic On-Chip Clocking - Industrial Trends,” Proc. of VLSI Test Symp., 2013.
[6] T.-Y. Li, S.-Y. Huang, H.-J. Hsu, C.-W. Tzeng, C.-T. Huang, J.-J. Liou, H.-P. Ma, P.-C. Huang, J.-C. Bor, C.-C. Tien, and M. Wang, and C.-W. Wu, “AC-Plus Scan Methodology for Small Delay Testing and Characterization,” IEEE Trans. on VLSI Systems (TVLSI), Vol. 21, No. 2, pp. 329-341, Feb. 2013.
[7] L. Y.-Z. Lin and C. H.-P. Wen, “Speed Binning with High-Quality Structural Patterns from Functional Timing Analysis (FTA),” Proc. of Asia and South Pacific Design Automation Conf., pp. 238-243, 2016.
[8] J. Zeng and M. Abadir, “On Correlating Structural Tests with Functional Tests for Speed Binning,” Proc. of Current and Defect Based Testing, pp. 79-83, 2004.
[9] N. Ahmed, M. Tehranipoor, and C. P. Ravikumar, “Enhanced Launch-off-Capture Transition Fault Testing,” Proc. of Int'l Test Conf., pp. 246-255, 2005.
[10] C.-W. Tzeng, S.-Y. Huang, P.-Y. Chao, and R.-T. Ding, "Parameterized All-Digital PLL Architecture and Its Compiler to Support Easy Process Migration," IEEE Trans. on VLSI Systems (TVLSI), Vol. 22, No. 3, pp. 621-630, March 2014.
[11] G. Mrugalski, J. Rajski, J. Rybak, J. Solecki, and J. Tyszer, “A Deterministic BIST Scheme Based on EDT-Compressed Test Patterns,” Proc. of Int'l Test Conf., pp. 1-8, 2015.
[12] M. Beck, O. Barondeau, M. Kaibel, F. Poehl, X. Lin, and R. Press, “Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality,” Proc. of Design Automation Test in Euro., pp. 56-61, 2005.
[13] R. Press and J. Boyer, “Easily implement PLL Clock Switching for At-Speed Test,” Chip Design Magazine, Feb.–Mar. 2006.
[14] X. X. Fan, Y. Hu, and L. T. Wang, “An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing,” Proc. Asian Test Symp., pp. 341-346, 2007.
[15] Y. Lee, S. Choi, S.-G. Kim, J.-A Lee, and K. Kim “Clock Multiplier Using Digital CMOS Standard Cells for High-Speed Digital Communication Systems,” Electronics Letters, Vol. 35, No. 24, pp. 2703-2704, Nov. 1999.
[16] C.E. Saaverdra, and Y. Zhang, “A Clock Frequency Doubler Using A Passive Integrator and Emitter-coupled Comparator Circuit,” Proc. Electrical and Computer Engineering, pp. 137-140, 2004.
[17] G. Wu, B. Yu, P. Gui, and P. Moreira, “Wide-range (25ns) and High-resolution (48.8ps) Clock Phase Shifter,” Electron Letters, vol. 49, no. 10, pp. 642-644, May 2013.
[18] J. Gu, J. Wu, D. Gu, M. Zhang, and L. Shi, “All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 4, pp. 760-764, April 2012.
[19] “Tessent On-Chip Clock Controller” in “Tessent Scan and ATPG User’s Manual version”, Mentor Graphics, Chapter 17, pp. 503-529, 2016.
[20] “CIC Reference Flow for Cell-based IC Design,” Chip Implementation Center, CIC, Taiwan, Document no. CIC- DSD-RD-08-01, 2008.
[21] P.-C. Huang, S.-Y. Huang, “Cell-Based Delay Locked Loop Compiler,” Proc. of Int'l SoC Design Conf., pp. 91-92, Oct. 2016.
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