對於先進的多核心晶片系統，我們必須確認其運作效能保有足夠的剩餘量，以使其能容忍諸如製程、電壓供應、溫度等等的變異。因此，有必要對每一邏輯合新加入內建速度分級測試(Built-In Speed Grading, BISG)之功能，使用者方能確認晶片是否能處於正常運作狀態，同時亦能作為動態供應電壓調控之依據。基本上，邏輯核心之速度分級(Speed Grading)方法是藉由不斷重複一樣的測試步驟，藉由改變每次的測試時脈頻率來得到待測核心之最快運作速度，舉例來說，此測試步驟可為針對延遲測試採取觸發後擷取(launch-off capture, LoC)之內建自測(Built-In Self-Test, BIST)。在此篇論文中，我們提出了一個可合成的寬頻時脈訊號產生方法，並將之應用於一個易於使用的速度分級方法。此時脈訊號產生方法主要包含了使用可合成的全數位鎖相迴路(All-Digital Phase-Locked Loop, ADPLL)、計數型除頻器以及倍頻電路。在90奈米製程下，其產生的寬頻時脈訊號頻率範圍將可含蓋五千萬赫茲至二十億赫茲，因此其可支援各種有著不同供應電壓、運作速度等等面向的邏輯核心。同時，因此時脈訊號產生方法為全細胞架構，其可容易地進行製程轉移。

In a modern multi-core SoC, the Built-In Speed Grading (BISG) of each logic core is often necessary in order to ensure an adequate operating margin for accommodating all kinds of variations (e.g., PVT variation) and to guide the dynamic VDD tuning process as well. In general, a speed grading method for a logic core can be performed by repeating a specific delay test session (e.g., built-in self-test with the latch-off capture scheme), with varying test clock frequencies to derive the maximum operating speed of a specific core under test. In this thesis, we propose an easy-to-use speed grading method featuring a wide-range synthesizable clock generation scheme so that it can support a logic core that could be used with different supply voltages and speeds in different application domains. The clock generation scheme mainly uses the fully synthesizable cell-based phase-locked loop (PLL), the counter-based frequency divider, and the frequency doubling circuit. The generated wide-range clock signal can span from 50MHz to 2GHz under 90nm technology. Since the circuit is fully cell-based, it is easy to do process migration.

Abstract i
摘要 ii
Content iii
List of Figures iv
List of Tables vi
Chapter 1 Introduction 1
1.1 Introduction 1
1.2 Thesis Organization 3
Chapter 2 Preliminaries 4
2.1 Generic Speed Grading Method 4
2.2 Related work 8
Chapter 3 Wide-Range Clock Signal Generation Scheme 10
3.1 Built-In Speed Grading Architecture 10
3.2 Specification of Generated Clock Signal 11
3.3 Proposed Clock Generation Scheme 13
3.4 Test Clock Signal Generation 24
3.5 Revisited Speed Grading Flow 25
Chapter 4 Experimental Results 27
4.1 Test Method Verification 27
4.2 Performance of Clock Generation 29
Chapter 5 Conclusion 33
References 34
Appendix 37

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