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研究生:李冠儀
研究生(外文):Li, Guan-Yi
論文名稱:射頻功率放大器之靜電放電防護設計
論文名稱(外文):On-Chip ESD Protection Design for Radio-Frequency Power Amplifier
指導教授:林群祐林群祐引用關係
指導教授(外文):Lin, Chun-Yu
學位類別:碩士
校院名稱:國立臺灣師範大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:108
中文關鍵詞:靜電放電防護矽控整流器串接二極體射頻功率放大器
外文關鍵詞:Electrostatic discharge protectionsilicon-controlled rectifierdiode stringpower amplifier
相關次數:
  • 被引用被引用:1
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  • 下載下載:35
  • 收藏至我的研究室書目清單書目收藏:0
本論文旨在利用嵌入矽控整流器之串接二極體來完成大訊號擺幅功率放大器的靜電放電防護設計,為了比較所提出的靜電放電防護電路的優劣性,也設計了串接二極體以及二極體觸發矽控整流器兩種靜電放電防護電路來提供比較。
為了驗證所提出的靜電放電防護電路在實際電路上的效能,本論文也設計了一個功率放大器電路來搭配此次所設計的三種靜電放電防護電路。實驗結果顯示,嵌入矽控整流器之串接二極體不會造成訊號的衰減及失真,且能夠有效的保護功率放大器。
在本論文中所設計的電路皆使用0.18-μm CMOS製程完成。並在實際的量測中發現,搭配串接二極體寄生矽控整流器的功率放大器電路能承受7 kV以上人體放電模式之靜電放電測試。
In this thesis, the diode string with embedded silicon-controlled rectifier (DSSCR) is designed to provide electrostatic discharge (ESD) protection of radio-frequency (RF) power amplifiers (PAs). To examine and evaluate the performance of the DSSCR, ESD protection circuits using the diode string (DS) and the diode-triggered SCR (DTSCR) are also designed and implemented for comparison with the proposed DSSCR protection circuit.
To validate the effectiveness of the designed ESD protection circuits, radio-frequency power amplifiers which equipped with the above-mentioned ESD protection circuits were designed and fabricated in this research. The measured results show that the protection circuit using DSSCR will not cause undesired signal degradation and distortion, and meanwhile can offer instant and effective protection to the RF PAs.
All of the ESD protection circuits designed in this thesis were fabricated using 0.18-um CMOS process. It is found in measurement that the RF PA equipped with the DSSCR protection circuit can bear 7-kV human-body-model (HBM) test.
摘要 I
Abstract II
Acknowledgment IV
Contents VII
Table Captions IX
Figure Captions X
Chapter 1 Introduction 1
1.1 Literature Survey and Research Motivation 1
1.2 Background of ESD 3
1.3 Test Standards of ESD 3
1.4 Traditional ESD Protection Design for Radio-Frequency Circuits 7
1.5 Introduction of Power Amplifiers 14
1.6 Thesis Organization 16
Chapter 2 Novel ESD Protection Design for Large-Swing Power Amplifier 17
2.1 Consideration of ESD Protection for Large-Swing Power Amplifier 17
2.2 Design of ESD Protection Devices 22
2.3 Measurement Methods and Results of ESD Protection Devices 30
2.4 Comparison of Traditional and Novel ESD Protection Devices 49
2.5 Summary of This Chapter 64
Chapter 3 2.4 GHz Power Amplifier with Novel ESD Protection Design 66
3.1 Reliability of CMOS Power Amplifier 66
3.2 Design of Power Amplifier 67
3.3 Architecture of the PA with ESD Protection Designs 75
3.4 Measured Results of the PAs with and without ESD Protection Circuits 78
3.5 Comparison between The Designed PAs with and without ESD Protection 89
3.6 Summary of This Chapter 95
Chapter 4 Conclusions and Future Works 97
4.1 Conclusion 97
4.2 Future Works 98
References 102
Vita 107
Publication List 108
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[6] C. Duvvury, “CDM qualification: Technology impact, testing nuances, and target levels”, IEW 2015.
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[14] S. Voldman, ESD: RF Technology and Circuits, John Wiley & Sons, 2006.
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[16] G. Chen and A. Wang, “Evaluating RF ESD protection design: An overview,” IEEE Physical and Failure Analysis of Integrated Circuits, pp. 205-208, July 2004.
[17] M.-D. Ker and K.-C. Hsu, “Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits,” IEEE Trans. Device and Materials Reliability, vol. 5, no. 2, pp. 235-249, Jun. 2005.
[18] S. Jang, L. Lin, S. Li, and H. Chen, “Dynamic triggering characteristics of SCR-type electrostatic discharge protection circuits,” Solid-State Elect., vol. 45, no. 7, pp. 1091-1097, Jul. 2001.
[19] M. Mergens, C. Russ, K. Verhaege, J. Armer, P. Jozwiak, R. Mohn, B. Keppens, and C. Trinh, “Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies,” IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 532-542, Sept. 2005.
[20] C.-Y. Lin and C.-Y. Chen, “Resistor-Triggered SCR Device for ESD Protection in High-Speed I/O Interface Circuits,” IEEE Electron Device Letters, no. 99, pp. 1-1, 2017.
[21] G.-Y. Li and C.-Y. Lin, “On-chip ESD protection design for radio-frequency power amplifier with large-swing-tolerance consideration,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 258-261, 2016.
[22] De-embedding and Embedding S-Parameter Networks Using a Vector Network Analyzer, Agilent, Application Note 1364-1, May, 2004.
[23] M.-D. Ker, C.-L. Hou, C.-Y. Chang, F.-T. Chu, "Correlation between transmission-line-pulsing I-V curve and human body model ESD level on low temperature poly-Si TFT devices," in 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. pp. 209-212, 2004.
[24] T. J. Maloney, "Evaluating TLP transients and HBM waveforms," in 31st Electrical Overstress/Electrostatic Discharge Symposium, pp. 1-9, 2009.
[25] M. Shrivastava, H. Gossner, M.S. Baghini, V.R. Rao, "Part I: On the behavior of STI-type DENMOS device under ESD conditions," IEEE Trans. on Electron Devices, vol. 57, no. 9, pp. 2235-2242, 2010.
[26] R. Ma, L. Wang, C. Zhang, F. Lu, Z. Dong, A. Wang, W. Lu,Y. Song, B. Zhao, "TLP and HBM ESD test correlation for power ICs, "IEEE International Conference of Electron Devices and Solid-State Circuits, pp. 1-2, 2013.
[27] M. Prabhu, J.-H. Lee, M.I. Natarajan, V. Kumar, R. Jain, T.-C. Tsai, L. Zhiqing, D. Thurmer, “Source of miscorrelation of product level HBM to TLP test results,” Electrical Overstress/Electrostatic Discharge Symposium, pp. 1-7, 2015.
[28] S.-L. Chen and M.-H. Lee, “Impacts of Leakage-Biasing Failure-Mode Identification in the Transmission-Line-Pulse Testing for Low-Voltage /High-Voltage MOSFET Components,” IEEE Transactions on Industry Applications, no. 99, pp. 1-1, 2017.
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[31] S. H. Voldman, G. Gerosa, V. P. Gross, N. Dickson, S. Furkay, and J. Slinkman, “Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors,” J. Electrostatics, vol. 38, nos. 1–2, pp. 3–31, Oct. 1996.
[32] L. Zhang; Y. Wang, and Y. He,” A novel insight into transient behaviors of diode-triggered SCRs under VF-TLP testing by 2D/3D simulations,” IEEE International Nanoelectronics Conference (INEC), pp. 1-2, 2016.
[33] J.-J. Liou, “Electrostatic discharge (ESD) protection of RF integrated circuits,” in Proc. IEEE Asia Pacific Conf. Circuits and Systems, Kaohsiung, Taiwan, R.O.C., Dec. 2012, pp. 460-462.
[34] Z. Shi, X. Wang, A. Wang, and Y. Cheng, “A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design technique,” in Proc. IEEE International Conference on ASIC, 2013.
[35] Y.-D. Shiu, B.-S. Huang, and M.-D. Ker, “CMOS power amplifier with ESD protection design merged in matching network,” IEEE International Conference on Electronics, Circuits and Systems, pp 825-828, 2007.
[36] X. Wang, X. Guan, S. Fan, H. Tang, H Zhao, L. Lin, Q. Fang, J. Liu, A. Wang, and L.-W. Yang, ” ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs,” IEEE Transactions on Industrial Electronics, vol.58, no. 7, pp. 2736-2743, 2011.
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