臺灣博碩士論文加值系統

在次世代COMS製程結點，改善次臨界擺幅、降低元件之操作電壓及功率損耗極為重要。當scaling 到Vt 不能再小時勢必也造成VDD無法再縮小，問題就發生在傳統的MOSFET的subthreshold swing 最小的物理極限為60mV/dec. ，而穿隧式場效電晶體在近幾年備受大眾的關注，因為穿隧電晶體係利用電子穿隧效應作為通道開關使S.S. 小於60mV/dec. 以及非常小的漏電流。降低VDD和較低的能源消耗的特性適合用於低功率元件。但是目前TFET在開的狀態時電流過低的問題，這將會限制住TFET的發展性。

因此，本論文研究方向是如何提高TFET電流與分析其特性。本文提出使用垂直方向的穿隧式電晶體結構並討論其機制，藉由使用磊晶技術增加穿隧面積已達到驅動電流的提升及優化元件參數提升TFET的性能，比較點穿隧型電晶體與面穿隧型電晶體來其特性。結果顯示面穿隧型電晶體開電流最大可以到達0.74μA/μm 且S.S. 在常溫下為97mV/dec，而點穿隧型電晶體的開電流只有0.07μA/μm但S.S. 在常溫下為76mV/dec。由於Trap-assisted Tunneling的機制導致開電流和次臨界擺幅沒有達到預期的好。因此使用電荷引汲技術並萃取其缺陷密度，發現面穿隧型電晶體的缺陷密度為2.5x1011(#/cm2)，主要分布在磊晶通道與源極的介面，而點穿隧型電晶的缺陷密度為1010(#/cm2)，分布介電層與通道/源極處。在未來工作中將製備出超薄的Si或是Ge磊晶層以達到高性能與低功耗操作之應用。

The steep subthreshold swing (S.S.) transistors may reduce power consumption and be a candidate of future generation technology node in CMOS industry. However, the subthreshold swing is limited by Boltzman tyranny 60 mV/dec, which restrictes the further reduced VDD. Tunneling FETs (TFETs) with S.S. < 60 mV/dec and low leakage has attracted lots of attention due to Zener band-to-band tunneling (BTBT). The characterists of reduced VDD and lower energy consumption are suitable for low power device applications. However, the low Ion current is a critical issue for TFET development.

The goal of this thesis is enhancement of the ON current for TFET. A TFET structure with vertical tunneling direction is proposed and the mechanism is discussed. In order to incresase the tunneling area for higher driving current by using epitaxial technology and the parameters of the devices is optimized to enhance the TFET performance. The results show the ON current and SS are as high as 0.74μA/μm and 97 mV/dec at room temperature, respectively. As compare with tranditional TFET (point TFET), ION 0.07μA/μm and S.S. 76 mV/dec are obtained. The ON current and S.S. are not as expected high due to Trap-assisted tunneling (TAT) mechanism. Therefore, the charge-pumping technique is performed to extract the trap density. It is found that the trap density of Face-TFET is 2.5x1011(#/cm2) and is mainly distributed at the interface between the epitaxial channel and source. And the trap density of Point-TFET is 1010(#/cm2) at the interface between dielectric and channel/source. The ultra-thin epitxial Si or Ge is required to achieve in future works, and makes high performance Face-TFET for low-power operation applications.

中文摘要…………………………………………………………………I
Abstract ……………………………………………………………III
致謝…………………………………………………………………………V
目錄…………………………………………………………………………VI
圖目錄……………………………………………………………………VIII
第一章 緒論
1-1 電晶體之微縮………………………………………………………………1
1-2 穿隧電晶體之操作原理……………………………………………………3
1-3 特性優化改善與設計………………………………………………………7
第二章 文獻回顧與論文導讀
2-1 平面型穿隧場效電晶體文獻……….…………………………………9
2-2 使用異質接面方式優化TFET…………………………………………11
2-3 垂直型穿隧場效電晶體文獻……………………………………………14
第三章 穿隧機制電晶體製作
3-1 實驗動機…………………………………………………………………19
3-2 平面型點穿隧電晶體製程與設計……………………………20
3-3 垂直型穿隧電晶體製程與設計…………………………………22
3-4 垂直型穿隧電晶體TEM之分析……………………………………33
3-5 穿隧電晶體電性分析與比較………………………………………35
3-6 Trap-assisted Tunneling model之探討…………………………37
3-7 Charge-pumping 量測與分析…………………………………40
3-8 穿隧電晶體之結論…………………………………………………46
第四章 結論
4-1 綜合討論…………………………………………………………………47
4-2 未來工作…………………………………………………………………49
參考文獻……………………………………………………………………52

[1] International Technology Roadmap for Semiconductors (ITRS)
[2] T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and < 60 mV/dec Subthreshold Slope, ” in IEDM Technical Digest, 2015, pp. 947-949.
[3] P. F Wang, “Complementary Tunneling-FETs (CTFET) in COS Technology, ” Technical University of Munich, Doctor Engineer, 10.11.2003ICSICT, pp. 16-20 (2008).
[4] N. Patel, A. Ramesh, and S. Mahapatra, “Drain Current Boosting of n-type Tunnel FET with Strained SiGe layer at source, ” IWJT, pp. 93-96 (2008).
[5] S. M. Sze, “Physics of Semiconductor Devices, ” Wiley , 1969
[6] A. Seabaugh, “Tunnel Field-Effect Transistor–Engubeer a Better Switch, ” IEEE IEDM short course, Dec. 4, 2011
[7] S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, “Germanium-Source Tunnel Field Effect Transistors with Record High ION/IOFF, ” in VLSI Symp. Tech. Dig., pp. 178-179, 2009.
[8] K. Joen, W.-Y. Lop, P. Patel, C. Y. Kang, J. Oh, A. Bowonder, C. Park, C. S. Park, C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J. King Liu, and C. Hu, “Si Tunnel Transistors with a Novel Silicided Source and 46 mV/dec Swing, ” in VLSI Symp. Tech. Dig., pp. 121-122, 2010.
[9] W. Y. Choi, J. Y. Song, J. D. Lee, Y. J. Park, and B.-G. Park, “70-nm Impact-Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs), ” in IEDM Technical Digest, 2005, pp. 955-958.
[10] A. Villalon, C. Le Royer, M. Casse, D. Cooper, B. Previtali, C. Tabone, J.-M. Hartmann, P. Perreau, P. Rivallin, J.-F. Damlencourt, F. Allain, F. Andrieu, O. Weber, O. Faynot, and T. Poiroux, “Strained Tunnel FETs with record ION: First Demonstration of ETSOI TFETs with SiGe channel and RSD, ” in VLSI Symp. Tech. Dig., pp. 49-50, 2012.
[11] T. Mori, Y. Morita, N. Miyata, S. Migita, K. Fukuda, M. Masahara, T. Yasuda, and H. Ota, “Band to band Tunneling Current Enhancement Utilizing Isoelectric Trap and its Application to TFETs, ” in VLSI Symp. Tech. Dig., pp. 74-75, 2014.
[12] H. G. Virani, R. B. Rao and A. Kottantharayil, “Investigation of Novel Si/SiGe Heterostructures and Gate Induced Source Tunneling for Improvement of p-Channel Tunnel Field-Effect Transistors, ” Japanese Journal of Applied Physics. Phys, vol. 49, 04DC12, 2010.
[13] C. Hu, D. Chou, P. Patel and A. Bowonder, “Green Transistor- A VDD Scaling Path for Future Low Power ICs, ” Internation Symposium on VLSI Technology, Systems and Applications, pp. 14-15, 2008.
[14] A. M. Walke, A. Vandooren, R. Rooyackers, D. Leonelli, A. Hikavyy, R. Loo, A. S. Verhulst, K. H. Kao, C. Huyghebaert, G. Groeseneken, V. R. Rao, K. K. Bhuwalke, M. M. Heyns, N. Collaert, and A. V.-Y. Thean, “Fabrication and Analysis of a Si/Si0.55Ge0.45 Heterojunction Line Tunnel FET, ” in IEEE Transactions on Electron Device, vol. 61, no. 3, pp. 707-715, 2014.
[15] Y. Morita, T. Mori, K. Fukuda, W. Mizubayashi, S. Mighita, T. Matsukawa, K. Endo, S. O’unchi, Y. Liu, M. Masahara, and H. Ota, “Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS Platform, ” in IEDM Technical Digest, 2014, pp. 243-246.
[16] R. N. Sajjad, and D. Antoniadis, “A compact model for tunnel FET for all operation regimes including trap assisted tunneling, ” Device Research Conference, 2016, pp. 66-67
[17] J. S. Brugler, and P. G. Jespers, “Charge pumping in MOS-devices, ” IEEE Transactions on Electron Devices, vol. 16, pp. 297-302, 1969.