本論文利用氧化物分子束磊晶系統 (Oxide MBE System) 成長氧化層，並製作成釔摻雜氧化鍺 (氧化鍺) / 鍺金氧半電容元件 (Metal – Oxide – Semiconductor Capacitor, MOSCAP) 進行量測與分析。我們改變釔摻雜氧化鍺的比例、成長時基板溫度並加入氧化層沉積後熱退火 (Post – Deposition Annealing, PDA) 與金屬沉積後熱退火 (Post – Metallization Annealing, PMA) 以得到最佳的元件電特性。
　　透過調整電子束蒸鍍之釔的電子束電流大小以改變不同比例的釔摻雜氧化鍺，我們發現釔成分與電導法 (Conductance Method) 所求得之介面缺陷密度 (Dit) 以及閘極漏電流有一最低點，當釔摻雜比例為27% 時 (Y/ (Ge+Y) = 27%) 有著最小的Dit和最小的閘極漏電流，且漏電流與的Dit成正相關。我們將27% 的釔摻雜氧化鍺進行PDA和PMA處理後，求得在室溫下量測釔摻雜氧化鍺/ 鍺金氧半電容元件之介面缺陷密度為 3.31 x 1011 (eV-1cm-2) ，閘極漏電流為6.2 × 10-9 (A/cm2)，遲滯為0.91 (V) 。
　　我們在釔摻雜氧化鍺與鍺之間多長一層0.5 nm的氧化鍺後經過PDA與PMA處理，氧化鍺與鍺基板的介面缺陷密度以及遲滯均下降，但閘極漏電流卻上升約八千倍到5.0 x 10-5 (A/cm2)。因此，我們認為氧化鍺不適合經過高溫處理。
　　我們改變基板溫度成長氧化層，成長溫度越高所製成的半導體元件介面缺陷越少，與經過PDA處理後的現象相同。400℃下成長釔摻雜氧化鍺/ 氧化鍺/ 鍺金氧半電容元件並經過PMA處理其室溫下量測之介面缺陷密度為2.2 x 1011 (eV-1cm-2) ，閘極漏電流為3.0 x 10-9 (A/cm2)，遲滯為0.28 (V) 。因此，我們推論400℃成長能使釔摻雜氧化鍺 (氧化鍺) 有著較佳的氧化層結構以及釔摻雜氧化鍺 (氧化鍺) 與鍺介面有較佳的鍵結，改善金氧半電容元件特性。

In this thesis, characteristics of Y-GeO2/ (GeO2) / Ge Metal-Oxide-Semiconductor capacitor (MOSCAP) grown by Oxide MBE System are investigated. To get the best performance of the device, Yttrium concentration and growth temperature of the oxide layer are adjusted and both post-deposition annealing (PDA) and post-metallization annealing (PMA) are carried out.
By controlling the emission current of the e-beam evaporation, the Yttrium concentration (xY) in Y-GeO2 is adjusted. It is found that there is a positive correlation between gate leakage current and Dit calculated by conductance method. Besides, there exists a minimum value of both interface traps density (Dit) and gate leakage current at a xY of 27 percent. The 27 percent Y-GeO2/ Ge MOSCAP is measured at room temperature, with Dit of 3.3 x 1011 (eV-1cm-2), gate leakage current of 6.2 x 10-9 (A/cm2), and hysteresis of 0.91 (V) after the PDA and PMA were carried out.
MOSCAP with an extra 0.5-nm-thick GeO2 between Y-GeO2 and Ge show lower Dit and hysteresis while the gate leakage current becomes about 8000 times larger to 5.0 x 10-5 (A/cm2) after PDA and PMA. Hence GeO2 is not suitable for high temperature treatments.
Growth temperature of the oxide layer is adjusted and it is find that the Dit becomes lower as the temperature goes higher, which is similar to the behavior after PDA treatment. The 400°C grown Y-GeO2/ (GeO2) / Ge MOSCAP after PMA treatment is measured at room temperature, with Dit of 2.2 x 1011 (eV-1cm-2), gate leakage current of 3.0 x 10-9 (A/cm2), and hysteresis of 0.28 (V). We infer that the structure of Y-GeO2 (GeO2) layer and its bonding between Ge interface is improved by 400°C high temperature growth, and hence behaves better MOSCAPs characteristics.

中文摘要 I
Abstract II
目錄 IV
圖目錄 VI
表目錄 IX
第一章、導論 1
1-1半導體元件發展 1
1-2 研究動機 2
1-2.1 鍺通道材料之介紹 2
1-2.2 高介電系數 (High-K) 之介紹與選擇 3
1-2.3 改善介面特性方法之介紹 5
1-2.4 鍺通道材料的優缺點統整與其他文獻比較 5
1-3 論文架構 6
第二章、儀器介紹與金氧半電容元件之理論 7
2-1 氧化層磊晶系統 (Oxide MBE System) 7
2-2 電子束熱蒸鍍系統 (E-Beam Thermal Evaporation) 9
2-3 X射線光電子能譜理論 (X - ray Photoelectron Spectroscopy Theory) 10
2-4 穿透式電子顯微鏡 (Transmission Electron Microscopy, TEM) 14
2-5金屬－氧化物－半導體元件電容之物理特性 15
2-5.1量測模型 15
2-5.2累積區 (Accumulation Region) 17
2-5.3 空乏區 (Depletion region) 18
2-5.4 反轉區 (Inversion region) 19
2-6氧化層缺陷對電容－電壓圖之影響 21
2-6.1累積區的電容頻散現象 (Accumulation Frequency Dispersion) 21
2-6.2弱反轉區之峰包現象 23
2-6.3氧化層缺陷遲滯現象 24
第三章、釔摻雜氧化鍺/ 鍺金氧半電容元件製作以及氧化層沉積後熱退火處理與金屬沉積後退火處理之特性分析 26
3-1元件製程步驟流程 26
3-2元件量測與分析 27
3-2.1不同比例之釔摻雜氧化鍺的電性量測與分析 27
3-2.2氧化層沉積後熱退火處理 (PDA) 與金屬沉積後退火處理 (PMA) 對元件的影響與分析 34
3-2.3穿隧式電子顯微鏡影像（Transmission Electron Microscopy, TEM, Image）與能量色散X-射線光譜(Energy Dispersive X-ray Analysis, EDX) 38
第四章、釔摻雜氧化鍺/ 氧化鍺/ 鍺金氧半電容元件製作以及氧化層沉積後熱退火處理與金屬沉積後退火處理之特性分析 43
4-1增加一層氧化鍺的元件製程步驟流程 43
4-2改變基板溫度成長氧化層 49
第五章、結論 54
第六章、參考文獻 55

[ 1 ] M. Sze, “ Physics of semiconductor devices ”, 3rd Ed, Wiley, p. 328, 2007.
[ 2 ] M. MayBerry, “ Enabling_Breakthroughs_Technology ”, p. 15, 2011.
[ 3 ] A. Toriumi, C. H. Lee, S. K. Wang, T. Tabata, M. Yoshida, D. D. Zhao, T. Nishimura, K. Kita, and K. Nagashio, “ Material Potential and Scalability Challenges of Germanium CMOS “, Tech. Dig. - Int. Electron Devices Meet. 646, 2011.
[ 4 ] G. Wilk, R. Wallace, et al., “ High – k gate dielectric : Current status and materials properties considerations “, J. Appl. Phys., 89, p. 5243, 2001.
[ 5 ] Q. Xie, D. Deduytsche, M. Schaekers, M. Caymax, A. Delabie, X.-P. Quc, and C. Detavernier, “Effective electrical passivation of Ge(100) for HfO2 gate dielectric layers using O2 plasma”, Electrochem. Solid-State Lett, 14, 5, pp. G20–G22, 2011.
[ 6 ] Eunice S. M. Goh, T. P. Chen, C. Q. Sun, and Y. C. Liu., “Thickness effect on the band gap and optical properties of germanium thin films“, J. Appl. Phys. 107, 024305, 2010.
[ 7 ] R. Pillarisetty, “Academic and industry research progress in germanium nanodevices”, Nature , 479, pp. 324–328, 2011.
[ 8 ] Sun J B, Yang Z W, Geng Y, Lu H L, Wu W R, Ye X D, Zhang W, Shi Y and Zhao Y., “Equivalent oxide thickness scaling of Al2O3/Ge metal oxide semiconductor capacitors with ozone post oxidation “, Chin. Phys. B 22, 067701, 2013.
[ 9 ] A. Dimoulas, G. Vellianitis, G. Mavrou, E. K. Evangelou, and A. Sotiropoulos, “Intrinsic carrier effects in HfO2–Ge metal–insulator–semiconductor capacitors“ , Appl. Phys. Lett. 86, 223507, 2005.
[ 10 ] I. Z. Mitrovic, M. Althobaiti, A. D. Weerakkody, V. R. Dhanak, W. M. Linhart, T. D. Veal, N. Sedghi, S. Hall, P. R. Chalker, D. Tsoutsou, and A. Dimoulas, “ Ge interface engineering using ultra-thin La2O3 and Y2O3 films: A study into the effect of deposition temperature “, J. Appl. Phys. 115, 114102, 2014.
[ 11 ] C. Chaneliere, S. Foue, J.L. Autran, R.A.B. Devine, N.P. Sandler, “ Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from a Ta(OC2H5)5 precursor “, J. Appl. Phys. 83, 4823, 1998.
[ 12 ] J. Robertson, “ Interface and defects of high-k oxides on silicon ”, Solid-State Electronics, 49, 3, 283, 2005.
[ 13 ] K. Prabhakaran, F. Maeda, Y. Watanabe, and T. Ogino, “ Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces ”, Appl. Phys. Lett. 76, 2244, 2000.
[ 14 ] T. Hosoi, K. Kutsuki, G. Okamoto, M. Saito, T. Shimura, and H. Watanabe, “ Origin of flatband voltage shift and unusual minority carrier generation in thermally grown GeO2 /Ge metal-oxide-semiconductor devices ”, Appl. Phys. Lett. 94, 202112, 2009.
[ 15 ] T. Nishimura, C. H. Lee, S. K. Wang, T. Tabata, K. Kita, K. Nagashio, and A. Toriumi, “ Desorption kinetics of GeO from GeO2 /Ge structure ”, Symp. VLSI Technol., Dig. Tech. Pap. 209, 2010.
[ 16 ] T. Nishimura, C. H. Lee, T. Tabata, S. K. Wang, K. Nagashio, K. Kita, and A. Toriumi, “ High-Electron-Mobility Ge n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with High-Pressure Oxidized Y2O3 ” , Appl. Phys. Express 4, 064201, 2011.
[ 17 ] C. Lu, C. H. Lee, W. Zhang, T. Nishimura, K. Nagashio, and A. Toriumi, “ Enhancement of thermal stability and water resistance in yttrium-doped GeO2/Ge gate stack ”, Appl. Phys. Lett. 104, 092909, 2014.
[ 18 ] S. J. Park, L. Bolotov, N. Uchida, and T. Tada, “ Distribution of free carriers near heavily-doped epitaxial surfaces of n-type Ge(100) upon HF and HCl treatments ”, AIP ADVANCES 5, 107219, 2015.
[ 19 ] J. Hu and H.-S. P. Wong, “Effect of annealing ambient and temperature on the electrical characteristics of atomic layer deposition Al2O3/In0.53Ga0.47As metal-oxide-semiconductor capacitors and MOSFETs”, J. Appl. Phys. 111, 044105, 2012.
[ 20 ] R.L. Chu, Y.C. Liu, W.C. Lee, T.D. Lin, M.L. Huang, T.W. Pi, J. Kwo, M. Hong, “Greatly improved interfacial passivation of in-situ high j dielectric deposition on freshly grown molecule beam epitaxy Ge epitaxial layer on Ge(100)”, Appl. Phys. Lett. 104, 202102, 2014.
[ 21 ] C.Y. Chang, C. Yokoyama, M. Takenaka, S. Takagi, “Impact of La2O3/InGaAs MOS Interfaces on the Performance of InGaAs MOSFETs”, IEEE Electron Device Lett. 64, 6, 2017.
[ 22 ] Y. Zheng, S. Hong, G. Psofogiannakis, G. B. Rayner, Jr., S. Datta, A. C. T. van Duin, R. Engel-Herbert, “Modeling and in Situ Probing of Surface Reactions in Atomic Layer Deposition”, ACS applied materials & interfaces, 9, 15848, 2017.
[ 23 ] C. Chou, H. Chang, C. Hsu, W. Yeh, C. Chien, “Low-Leakage Tetragonal ZrO2 (EOT < 1 nm) With In Situ Plasma Interfacial Passivation on Germanium”, IEEE Electron Device Lett. 37, 138, 2016.
[ 24 ] W. J. Carter, G. K. Schweitzer and T. Carlson, “Experimental evaluation of a simple model for quantitative analysis in X-ray photoelectron spectroscopy”, J. Electron Spectrosc., 5, 827, 1974.
[ 25 ] N. Fairley, “CasaXPS manual 2. 3. 15: Introduction to XPS and AES”, Casa Software Ltd., 2009.
[ 26 ] J. F. Moulder, W. F. Stickle, P. E. Sobol and K. D. Bomben, “Handbook of x-ray photoelectron spectroscopy”, Perkin-Elmer Corporation Physical Electronics Division, 1992.
[ 27 ] Y. Yuan, L. Wang, B. Yu, B. Shin, J. Ahn, P. C. McIntyre, P. M. Asbeck, M. J. W. Rodwell, and Y. Taur, “A distributed model for border traps in Al2O3–InGaAs MOS devices”, IEEE Electron Device Lett., 32, 4, 485, 2011.
[ 28 ] N. Taoka, K. Ikeda, Y. Yamashita, N. Sugiyama, and S.-I. Takagi, “Effects of ambient conditions in thermal treatment for Ge (100) surfaces on Ge- MIS interface properties”, Semicond. Sci. Technol., 22, S114– S117, 2007.
[ 29 ] K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. M. Heyns, T. Krishnamohan, and K. Saraswat, “On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates”, IEEE Trans. Electron Devices, 55, 547, 2008.
[ 30 ] W. Shockley and W. T. Read, Jr., "Statistics of recombinations of holes and electrons," Phys. Rev., 87, 835, 1952.
[ 31 ] K. Tanaka, R. Zhang, M. Takenaka, and S. Takagi, "Quantitative evaluation of slow traps near Ge MOS interfaces by using time response of MOS capacitance", Jpn. J. Appl. Phys. 54, 04DA02, 2015.
[ 32 ] E. H. Nicollian and A. Goetzberger, “The Si‐SiO2 Interface—Electrical Properties as Determined by the Metal‐Insulator‐Silicon Conductance Technique”, Bell Syst. Tech. J., 46, 1055, 1967.
[ 33 ] C. Svensson and I. Lundstrõm, “Trap-assisted charge injection in MNOS structures”, J. Appl. Phys. 44, 4657, 1973.
[ 34 ] C. H. Lee, C. Lu, T. Tabata, W. F. Zhang, T. Nishimura, K. Nagashio, and A. Toriumi, “Oxygen Potential Engineering of Interfacial Layer for Deep Sub-nm EOT High-k Gate Stacks on Ge”, IEDM Tech. Dig., p. 40, 2013.
[ 35 ] C. Lu, C. H. Lee, W. Zhang, T. Nishimura, K. Nagashio, and A. Toriumi, “ Structural and thermodynamic consideration of metal oxide doped GeO2 for gate stack formation on germanium ”, J. Appl. Phys. 116, 174103, 2014.