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研究生:王冠勛
研究生(外文):Guan-Shiun Wang
論文名稱:釔摻雜氧化鍺/ 氧化鍺/ 鍺金氧半電容元件介面特性之研究
論文名稱(外文):The research on the interface properties of Y-GeO2/ (GeO2) / Ge MOSCAP
指導教授:林浩雄林浩雄引用關係
指導教授(外文):Hao-Hsiung Lin
口試日期:2017-07-29
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:光電工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:中文
論文頁數:58
中文關鍵詞:釔摻雜氧化鍺氧化物 (金屬) 沉積熱退火處理金氧半電容元件
外文關鍵詞:GermaniumYttrium-doped Germanium OxidePDAPMAMOSCAPs
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 本論文利用氧化物分子束磊晶系統 (Oxide MBE System) 成長氧化層,並製作成釔摻雜氧化鍺 (氧化鍺) / 鍺金氧半電容元件 (Metal – Oxide – Semiconductor Capacitor, MOSCAP) 進行量測與分析。我們改變釔摻雜氧化鍺的比例、成長時基板溫度並加入氧化層沉積後熱退火 (Post – Deposition Annealing, PDA) 與金屬沉積後熱退火 (Post – Metallization Annealing, PMA) 以得到最佳的元件電特性。
  透過調整電子束蒸鍍之釔的電子束電流大小以改變不同比例的釔摻雜氧化鍺,我們發現釔成分與電導法 (Conductance Method) 所求得之介面缺陷密度 (Dit) 以及閘極漏電流有一最低點,當釔摻雜比例為27% 時 (Y/ (Ge+Y) = 27%) 有著最小的Dit和最小的閘極漏電流,且漏電流與的Dit成正相關。我們將27% 的釔摻雜氧化鍺進行PDA和PMA處理後,求得在室溫下量測釔摻雜氧化鍺/ 鍺金氧半電容元件之介面缺陷密度為 3.31 x 1011 (eV-1cm-2) ,閘極漏電流為6.2 × 10-9 (A/cm2),遲滯為0.91 (V) 。
  我們在釔摻雜氧化鍺與鍺之間多長一層0.5 nm的氧化鍺後經過PDA與PMA處理,氧化鍺與鍺基板的介面缺陷密度以及遲滯均下降,但閘極漏電流卻上升約八千倍到5.0 x 10-5 (A/cm2)。因此,我們認為氧化鍺不適合經過高溫處理。
  我們改變基板溫度成長氧化層,成長溫度越高所製成的半導體元件介面缺陷越少,與經過PDA處理後的現象相同。400℃下成長釔摻雜氧化鍺/ 氧化鍺/ 鍺金氧半電容元件並經過PMA處理其室溫下量測之介面缺陷密度為2.2 x 1011 (eV-1cm-2) ,閘極漏電流為3.0 x 10-9 (A/cm2),遲滯為0.28 (V) 。因此,我們推論400℃成長能使釔摻雜氧化鍺 (氧化鍺) 有著較佳的氧化層結構以及釔摻雜氧化鍺 (氧化鍺) 與鍺介面有較佳的鍵結,改善金氧半電容元件特性。
In this thesis, characteristics of Y-GeO2/ (GeO2) / Ge Metal-Oxide-Semiconductor capacitor (MOSCAP) grown by Oxide MBE System are investigated. To get the best performance of the device, Yttrium concentration and growth temperature of the oxide layer are adjusted and both post-deposition annealing (PDA) and post-metallization annealing (PMA) are carried out.
By controlling the emission current of the e-beam evaporation, the Yttrium concentration (xY) in Y-GeO2 is adjusted. It is found that there is a positive correlation between gate leakage current and Dit calculated by conductance method. Besides, there exists a minimum value of both interface traps density (Dit) and gate leakage current at a xY of 27 percent. The 27 percent Y-GeO2/ Ge MOSCAP is measured at room temperature, with Dit of 3.3 x 1011 (eV-1cm-2), gate leakage current of 6.2 x 10-9 (A/cm2), and hysteresis of 0.91 (V) after the PDA and PMA were carried out.
MOSCAP with an extra 0.5-nm-thick GeO2 between Y-GeO2 and Ge show lower Dit and hysteresis while the gate leakage current becomes about 8000 times larger to 5.0 x 10-5 (A/cm2) after PDA and PMA. Hence GeO2 is not suitable for high temperature treatments.
Growth temperature of the oxide layer is adjusted and it is find that the Dit becomes lower as the temperature goes higher, which is similar to the behavior after PDA treatment. The 400°C grown Y-GeO2/ (GeO2) / Ge MOSCAP after PMA treatment is measured at room temperature, with Dit of 2.2 x 1011 (eV-1cm-2), gate leakage current of 3.0 x 10-9 (A/cm2), and hysteresis of 0.28 (V). We infer that the structure of Y-GeO2 (GeO2) layer and its bonding between Ge interface is improved by 400°C high temperature growth, and hence behaves better MOSCAPs characteristics.
中文摘要 I
Abstract II
目錄 IV
圖目錄 VI
表目錄 IX
第一章、導論 1
1-1半導體元件發展 1
1-2 研究動機 2
1-2.1 鍺通道材料之介紹 2
1-2.2 高介電系數 (High-K) 之介紹與選擇 3
1-2.3 改善介面特性方法之介紹 5
1-2.4 鍺通道材料的優缺點統整與其他文獻比較 5
1-3 論文架構 6
第二章、儀器介紹與金氧半電容元件之理論 7
2-1 氧化層磊晶系統 (Oxide MBE System) 7
2-2 電子束熱蒸鍍系統 (E-Beam Thermal Evaporation) 9
2-3 X射線光電子能譜理論 (X - ray Photoelectron Spectroscopy Theory) 10
2-4 穿透式電子顯微鏡 (Transmission Electron Microscopy, TEM) 14
2-5金屬-氧化物-半導體元件電容之物理特性 15
2-5.1量測模型 15
2-5.2累積區 (Accumulation Region) 17
2-5.3 空乏區 (Depletion region) 18
2-5.4 反轉區 (Inversion region) 19
2-6氧化層缺陷對電容-電壓圖之影響 21
2-6.1累積區的電容頻散現象 (Accumulation Frequency Dispersion) 21
2-6.2弱反轉區之峰包現象 23
2-6.3氧化層缺陷遲滯現象 24
第三章、釔摻雜氧化鍺/ 鍺金氧半電容元件製作以及氧化層沉積後熱退火處理與金屬沉積後退火處理之特性分析 26
3-1元件製程步驟流程 26
3-2元件量測與分析 27
3-2.1不同比例之釔摻雜氧化鍺的電性量測與分析 27
3-2.2氧化層沉積後熱退火處理 (PDA) 與金屬沉積後退火處理 (PMA) 對元件的影響與分析 34
3-2.3穿隧式電子顯微鏡影像(Transmission Electron Microscopy, TEM, Image)與能量色散X-射線光譜(Energy Dispersive X-ray Analysis, EDX) 38
第四章、釔摻雜氧化鍺/ 氧化鍺/ 鍺金氧半電容元件製作以及氧化層沉積後熱退火處理與金屬沉積後退火處理之特性分析 43
4-1增加一層氧化鍺的元件製程步驟流程 43
4-2改變基板溫度成長氧化層 49
第五章、結論 54
第六章、參考文獻 55
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