臺灣博碩士論文加值系統

新興的存儲類存儲器(SCM)技術(如相變存儲器,STT-RAM,RRAM,3D XPoint等)承諾具有DRAM級數量級的字節可尋址持久存儲器,具有彌合緩慢之 間的差距,持久存儲和快速,易失性存儲器,表明包含在存儲器總線上將這些下 一代非易失性存儲器(NVM)與DRAM一起放置。然而,持久存儲器提出了新的 挑戰,系統需要在系統故障或功率損耗的情況下保證存儲器的一致狀態,沒有這 種可靠性,非易失性存儲器將僅適合作為瞬態數據存儲或緩存層。
現在最常見的一致性支持技術是寫時復制和日記功能。他們都有自己的利弊, 但是他們有同樣的問題:他們依靠使用緩慢的軟件拷貝,以保證發生電源丟失或 系統崩潰時的一致性,這主要由數據副本組成,浪費當非易失性存儲器連接到存 儲器總線時的存儲器帶寬,NVM具有DRAM性能和低延遲的優勢。因此,一致性 技術無法利用NVM功能,浪費NVM性能。因此,為了提高當前的一致性支持技 術效率,我們提出了一個內部複製機制TileClone。
為了利用NVM潛力,需要NVM感知的一致性支持。儘管如此,已經有現有 的硬件支持的DRAM複製加速機制,例如RowClone,這是一種提供無需CPU干 預的行數據複製的機制。然而,NVM存在不同的特徵和約束,需要考慮到, 直接使用DRAM機制來加速NVM的崩潰一致性是不重要的,因此我們提出 了TileClone,一種用於NVM的硬件技術,用於NVM數據拷貝以加速日誌記錄檢 查點階段,將這一階段擺脫關鍵路徑,直接導致加速碰撞一致性技術。

Emerging Storage Class Memory (SCM) technologies such as phase-change memory, STT-RAMs, RRAM, 3D XPoint, etc. promise byte-addressable persistent memory with performance within an order of magnitude of DRAM. With the potential to bridge the gap between slow persistent storage and fast volatile memory, these next- generation non-volatile memories (NVMs) had been suggested to be put alongside DRAM on the memory bus. Nevertheless, persistent memory arises a new challenge, systems need to guarantee a consistent state of the memory in case of system failure or power loss. However, reliability support mechanisms are designed with the slow block-based device as the persistent storage. Hereby, these mechanisms can overwhelm the low latency that NVM should provide. Nevertheless, without this reliability, non-volatile memories will only be suitable as a transient data store or as a caching layer.
Nowadays most common consistency support techniques are Copy-On-Write and Journaling. These consistency techniques have their own pros and cons, however, they have a common issue: they rely on the use of slow software copy in order to guarantee consistency on the event of power loss or a system crash. These software copies are mostly composed of data movement that waste memory bandwidth when non-volatile memories are connected to the memory bus, hindering NVM advantage of DRAM-like performance and low latency on data movement. As a result, consistency techniques are unable to take advantage of NVM DRAM-like advantages, squandering NVM performance.
Therefore, to enhance current consistency support techniques, we propose an in-nvm copy mechanism, TileClone. Despite that, there is already existing hard- ware supported copy acceleration mechanism for the DRAM, such as RowClone, a mechanism providing row data copy without CPU intervention. Nevertheless, NVM present different characteristics and constraints that need to be taken into consideration. Directly employing DRAM mechanism to accelerate crash consistency on NVM is non-trivial. Unmanaged copy of data could end up delaying normal read/write operations, degrading overall performance. Therefore we propose Tile- Clone, a hardware technique for NVM providing In-NVM data copy to accelerate journaling checkpoint stage, moving this stage o the critical path and as a direct result, accelerating the crash consistency technique. Our mechanism can reduce up to 49.8% of the memory bus traffic.

目次
Acknowledgments i
Abstract iii
List of Figures ix
List of Tables xi
Chapter 1 Introduction 1
Chapter 2 Background 5
2.0.1 Data Movement on Consistency Techniques 5
2.0.2 NVM Architecture 8
Chapter 3 TileClone 11
3.1 TileCloneOverview11
3.1.1 TileClone Copy Modes 13
3.1.2 Tile-Aware Data and Journal Area Partition 14
3.1.3 Tile-Aware Journal Selection 16
3.1.4 TileClone ISA Support 20
3.1.5 Data to Journal Mapping Information 21
3.1.6 In-NVM Checkpoint 22
Chapter 4 Evaluation 25
4.0.1 Experimental Setup 26
4.0.2 Experimental Result 28
Chapter 5 Related Work 39
Chapter 6 Conclusion 40
Bibliography 41

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