臺灣博碩士論文加值系統

本論文實現了適用於可調動式中頻接收機之高頻前端電路，電路包含了低雜訊放大器、第一級的降頻混頻器還有一個I/Q 的混頻器做為第二級的降頻混頻器。
在高頻前端電路的第一級為一個可調增益式的低雜訊放大器。該可調式增益為避免輸入訊號過大而造成電路飽和。本作品使用台積電40 奈米製程，系統功耗為15毫瓦，在頻率為360 億赫茲時有最大的增益為10 dB, 噪音雜訊為5.8 dB。增益調整的範圍為10 dB。
緊接在後的是一個將訊號由頻率 360 億赫茲降轉到70 億赫茲的降頻混頻器。
並且採用分流電流的方式來降低雜訊指數。本作品使用台積電40 奈米製程，系統
功耗為4.5 毫瓦，由於一些EM 模型上的不確定造成增益最大為-20.8 dB，輸入1
dB 增益壓縮點為 6 dBm。
最後一級為一個具 I/Q 相位調變的降頻混器，該混頻器將訊號由頻率約70 億
赫茲降轉到 10 億赫茲以內。此外，還實現了一個除頻器來產生所需的四個相位。
本作品使用台積電40 奈米製程，系統功耗包含量測所需的緩衝器為10 毫瓦，增
益最大為17 dB，輸入1 dB 增益壓縮點為 -14 dBm。

In this thesis, an RF front-end which is a sliding IF receiver including a low-noise amplifier, a first stage down-conversion mixer and an I/Q mixer as the second stage are proposed in a 1.1-V supply. The first stage of proposed RF front-end presents a variable gain control low noise amplifier to keep different input magnitude from saturation of circuit. This work is fabricated in TSMC 40-nm CMOS technology. The total power consumption is 15 mW, the highest gain is 10 dB and noise figure is 5.8 dB at 36 GHz. The variable gain control can adjust the gain more than 10 dB.
The following stage is a down-conversion mixer which converts frequency from 36 GHz to 7 GHz. The work introduces a current-bleeding technique to improve the noise figure. This work is fabricated in TSMC 40-nm CMOS technology. The total power consumption is 4.5 mW. With some EM model uncertain, the conversion gain is -20.8 dB
and input P1dB is 6 dBm.
The latest stage is an I/Q down-conversion mixer which converts frequency from 7 GHz to below 1 GHz. Besides, to generate four phase, a CML divider is also implemented. This work is fabricated in TSMC 40 nm CMOS technology. The total power consumption of I/Q mixer including the buffer for measurement is 10 mW. The conversion gain is 17 dB, NF is 8.88 dB and the input P1dB is -14 dBm.

中文審定書 i
英文審定書 iii
摘要 vii
Abstract ix
List of Figures xiii
List of Tables xvii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Overview 3
Chapter 2 Introduction to RF Front-end 5
2.1 Fundamentals of RF Front-end Systems 5
2.1.1 Noise Due to Frequency Transforming 6
2.2 Architectures of RF Front-end Circuits 7
2.2.1 Direct-conversion Front-end Circuits 7
2.2.2 RF Front-end with Dual IF 8
2.2.3 RF Front-end with Quadrature Down-conversion 9
2.2.4 RF Front-end without LNA 10
2.3 Summary and Specification of the Each Stage 11
Chapter 3 Proposed Low-Noise Amplifier with Positive-Feedback Technique and Variable-gain Control 13
3.1 Introduction 13
3.2 System Architecture 14
3.3 Circuit Implementation 17
3.3.1 Inductive-peaking Technique 17
3.3.2 Analysis of the Inductive-peaking Technique 20
3.3.3 Analysis of Gain Control Mechanism 22
3.3.4 Simulation Results Summary 26
3.4 Experimental Results 27
3.4.1 Die Photo 27
3.4.2 Measurement Environment Setup 27
3.4.3 PCB Design 29
3.4.4 Measured Results 30
3.5 Discussion 36
Chapter 4 Proposed 1st-stage Down-Conversion Mixer with Current-Bleeding Technique 39
4.1 Introduction 39
4.2 Proposed Architecture 41
4.3 Analysis of Noise in Mixer 42
4.3.1 Noise from the RF Stage 44
4.3.2 Thermal Noise Generated in the Switching Pair 45
4.4 Circuit Implementation 48
4.4.1 Linearity and Gain Analysis of Mixer with Current-Bleeding Source 48
4.4.2 RF and LO Balun 52
4.4.3 Simulation Results Summary 55
4.5 Experimental Results 57
4.5.1 Die Photo 57
4.5.2 Measurement Environment Setup 58
4.5.3 PCB Design 59
4.5.4 Measured Results 60
4.5.5 Discussion 65
Chapter 5 Proposed 2nd-stage Down-Conversion Mixer with Source-driven Technique 67
5.1 Introduction 67
5.2 Proposed Architecture 69
5.3 Circuit Implementation 71
5.3.1 Source-driven Mixer 71
5.3.2 RF and LO Balun 74
5.3.3 Simulation Results Summary 78
5.4 Experimental Results 80
5.4.1 Die Photo 80
5.4.2 Measurement Environment Setup 80
5.4.3 PCB Design 83
5.4.4 Measured Results 84
5.5 Discussion 91
Chapter 6 Conclusions and Future Works 93
6.1 Conclusions 93
6.2 Future Works 93
References 95

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