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研究生:翁翊軒
研究生(外文):I-Hsieh Wong
論文名稱:鍺通道平面式與環繞式閘極場效應電晶體之製備與特性分析
論文名稱(外文):Fabrication and Characterization of Planar and Gate-all-around Germanium Channel MOSFETs
指導教授:劉致為
口試日期:2017-07-08
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:125
中文關鍵詞:鍺通道雷射熱退火環繞式閘極電晶體無接面電晶體載子遷移率應變響應溫度依存性
外文關鍵詞:Ge channelGate-all-around transistorJunctionless transistorCarrier mobilityThreshold voltageStrain responseTemperature dependence
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在本篇論文中著重於高遷移率鍺通道電晶體之製作與特性分析,分別探討p型平面式電晶體與n型環繞式閘極電晶體之臨界電壓與載子遷移率溫度依存性、遷移率之應變響應及相關製程整合與模組技術。
當電晶體尺寸持續微縮後,使用具有高遷移率的通道材料來增加驅動電流或降低能耗是未來半導體元件發展的方向之一,並搭配三維電晶體結構以增加閘極控制以改善短通道效應、降低漏電及能耗,並增加單位面積驅動電流。鍺已被整合於目前之主流矽基半導體製程中,並可利用化學氣相沉積磊晶技術整合於大尺寸矽基板並降低製程成本。同時鍺具有較接近之電子/電洞遷移率,有利於實現鍺基互補式金氧半場效電晶體,更使得鍺成為未來最重要的通道材料之一。然而,鍺要實現在互補式金氧半電晶體上還有一些困難需要克服,例如低缺陷密度及高摻雜濃度的鍺磊晶層成長、低源/汲極串聯電阻以及三維電晶體之蝕刻技術等,都是現在必須解決的問題。
於平面式p型鍺金氧半場效電晶體元件上,利用高品質氧化鋁/二氧化鍺作為閘極氧化層材料以降低介面缺陷密度並提高載子遷移率,再利用鎳鍺合金作為源極以及汲極電極金屬搭配兩階段離子佈植技術以降低串聯電阻並進一步提高操作電流。利用製作於(100)及(110)晶圓上之元件以萃取載子遷移率,(110)/<110>之p型鍺通道電晶體因具有較(100)/<110>電晶體為低之電洞等效質量,因此具有較高之電洞遷移率(528 cm2/V-s)。為了進一步提高載子遷移率,本研究中利用外加機械應力的方式以降低電洞等效質量,(100)/<110>電晶體在外加應力後具有較大之應變響應,與文獻中之理論預測相符。本研究並利用低溫量測的方式分析元件載子遷移率之散射機制,以驗證電洞遷移率於高電場除表面粗糙散射外仍有聲子散射的影響。由分析臨界電壓之溫度依存性並搭配理論,並額外考慮介面缺陷密度之影響,可提出理論模型解釋鍺基電晶體具有較大之臨界電壓變化並與實驗相驗證。
在三維電晶體方面,利用具有較高電子遷移率之鍺通道製作電晶體,搭配化學氣相沉積磊晶之內摻雜技術及雷射熱退火技術可以在矽基板上成長品質良好且具有伸張應變之鍺磊晶層,其磷摻雜活化濃度可達2E20 cm-3。利用良好的磊晶層技術搭配選擇性差異蝕刻技術,可實現環繞式閘極電晶體結構,並降低矽鍺接面缺陷對電晶體電性之影響。另外選擇無接面之電晶體架構設計以降低整合複雜度,並避免使用離子佈植所產生的額外缺陷。在通道長度250奈米及等效氧化層厚度2.2 奈米的結構下,n型鍺通道無接面環繞式閘極電晶體具有828 uA/um的高操作電流(VOV =1.5 V, VDS = 2 V)。
當元件尺寸持續微縮,電晶體的電流除了由通道電組控制之外,有大部分被源汲極串聯電阻所限制。為了降電阻效應,本研究採用提高源汲極摻雜濃度的方式並整合鎳鍺合金電極。利用選擇性雷射熱退火的方式可在不改變通道摻雜濃度的前提下提高源汲極摻雜濃度,以降低半導體電阻及金屬/半導體接面電阻而使電流獲得提升。搭配通道長度的微縮(Lch = 60 nm),其操作電流可達1146 uA/um (VOV = VDS = 1 V),並可進一步藉由外加應力的方式提升至1235 uA/um (VOV = VDS = 1 V)。本研究並利用改變環境溫度及脈衝量測之方式分析無接面電晶體之遷移率溫度依存性及其自發熱效應,證明在無接面電晶體中載子遷移率主要由庫倫散射所主導。此外也利用實驗驗證無接面電晶體載子遷移率之隨伸張應變具有增益的特性並萃取元件低頻雜訊之表現,且利用TCAD模擬方式並考慮7奈米元件之量子效應以分析載子之二維分布並與實驗相驗證。
In this dissertation, the fabrication and electrical characterization of germanium channel planar pMOSFETs and gate-all-around (GAA) nFETs in terms of parasitic resistance reduction, process integration, temperature dependence of mobility/ threshold voltage extraction, and strain response are investigated.
As the device keeps scaling down, the high mobility channels are proposed to enhance drive current and reduce power consumption. With the integration of 3D device architectures (FinFET, tri-gates, and GAA FETs), the devices provide good gate controllability to suppress short channel effects, reduced leakage and power consumption and increased current density. Ge has been integrated with modern Si process and can be epitaxially grown on large scale Si wafer by chemical vapor deposition (CVD) to reduce the cost. The highest hole mobility and high electron mobility of Ge are benefit for the integration of CMOS circuit, which make Ge a promising candidate to replace Si as channel material.
In the first part of this dissertation, the high mobility Ge planar pFETs are fabricated and characterized. The high quality Al2O3/GeO2 gate stack provides low density of interface trap (Dit), which leads to suppressed impurity scattering and mobility enhancement at low field region. To further boost the performance by reducing parasitic resistance, two-step implantation and NiGe S/D contact metal are integrated on Ge substrates. For pMOSFETs, the <110> channel direction on the (110) Ge substrates offers the highest hole mobility theoretically among all substrate/channel configurations. The demonstrated Ge pFETs have the reduced S/d parasitic resistance and peak hole mobility of 528 cm2/V-s. To further enhance the drive current, the uniaxial tensile strain is applied perpendicular to the channel direction by wafer bending. Due to the Poisson ratio, the compressive strain parallel to the channel can be generated. The (100) device has a larger strain response than the (110) device which is consistent with theoretical calculation.
In the second part of this dissertation, the temperature dependence of mobility and threshold voltage of Ge planar pFETs are investigated by low temperature measurement. The carrier mobility of Ge pFETs is dominated by impurity scattering at low field and increased with increasing temperature. At high field region, the mobility decreases with increasing temperature, indicating that phonon scattering is dominating. For the temperature dependent threshold voltage modeling, the effect of interface charge increase is considered due to the high Dit in Ge MOSFETs, and is verified with experimental data.
Next, the high performance Ge junctionless nGAAFETs with high drive and Ion/Ioff are fabricated and characterized. The CVD-grown epi-Ge on SOI with low defect density and tensile strain is achieved by in-situ phosphorus doping and laser annealing and the active doping concentration reaches 2E20 cm-3. The selective anisotropic etching was performed to remove the defective Ge near Ge/Si interface which degrade IV characteristics and to form GAA structure. For the operation mode, the junctionless (JL) transistor is used to prevent defect generation and doping diffusion issues of ion implantation and simplify the process. With channel length (Lch) of 250 nm and equivalent oxide thickness of 2.2 nm, the fabricated JL Ge nGAAFETs have high drive current of 828 uA/um and Ion/Ioff of 105.
Finally, parasitic resistance reduction of Ge JL nGAAFETs by selective laser annealing and NiGe contact metal is investigated. In highly scaled transistor, the drive current is limited by parasitic resistance. To reduce the resistance by simply raise the S/D doping level, the selective laser annealing is performed to re-activate the dopant at S/D region and maintain good gate stack quality and relative low doping concentration at channel simultaneously. With scaled Lch of 60 nm, the drive current of Ge JL nGAAFETs reaches 1146 uA/um (VOV = VDS = 1 V) and can be further enhance to 1235 uA/um by applying external strain. The mobility enhancement of JL nGAAFETs with self-heating effect observed by pulse-IV and low temperature measurement indicates that the mobility is dominated by impurity scattering.
Chapter 1 Introduction
1.1 Motivation..................................................................................1
1.2 Thesis organization.................................................................4
1.3 References..................................................................................6

Chapter 2 Fabrication and Characterization of Planar Ge (110) and (100) pMOSFETs
2.1 Introduction.............................................................................. 8
2.2 Fabrication of Planar Ge pMOSFETs...............................10
2.2.1 MISCAPs Fabrication and Characterizations..........10
2.2.2 Source/drain Engineering…..........................................15
2.2.3 MOSFETs Fabrication......................................................22
2.3 Planar Ge pMOSFETs Characterizations........................23
2.3.1 Current-voltage characteristics...................................23
2.3.2 Parasitic resistance extraction.....................................26
2.3.3 Mobility extraction...........................................................28
2.4 Strain Response of Ge (100) and (110)
pMOSFETs………………….........................................................31
2.4.1 Experimental setup.........................................................31
2.4.2 Mobility enhancement by external strain..............32
2.5 Summary...................................................................................35
2.6 References................................................................................36

Chapter 3 Analysis of Low Temperature Characteristics of Planar Ge pMOSFETs
3.1 Introduction .............................................................................41
3.2 Low Temperature IV Characteristics...............................42
3.2.1 Temperature dependence of subthreshold
characteristics...............................................................42
3.2.2 Temperature dependence of hole mobility......44
3.3 Temperature dependence of threshold voltage .......47
3.3.1 Threshold voltage shift extraction........................47
3.3.2 Modeling of temperature dependence of
threshold voltage.......................................................48
3.4 Summary....................................................................................52
3.5 References.................................................................................53

Chapter 4 Fabrication and Characterization of Ge Junctionless Gate-all-around nFETs
4.1 Introduction.............................................................................55
4.2 Epitaxy of heavily doped nGe and material
characterization......................................................................56
4.2.1 CVD growth of heavily doped nGe on Si
substrates............................................................................56
4.2.2 Doping concentration enhancement and defect
density reduction by laser annealing.......................60
4.3 Fabrication of Ge junctionless gate-all-around
nFETs ..........................................................................................65
4.3.1 Channel formation by selective etching....................65
4.3.2 Low equivalent-oxide-thickness gate stack
formation...............................................................................67
4.3.3 Optimization of channel doping concentration…..71
4.3.4 Device fabrication...............................................................73
4.4 Characterization of Ge junctionless gate-all-around
nFETs...........................................................................................74
4.4.1 Current-voltage characteristics.....................................74
4.4.2 Mobility extraction.............................................................78
4.4.3 Non-uniform channel effect...........................................81
4.5 Summary....................................................................................82
4.6 References.................................................................................82

Chapter 5 Doping Profile Optimization of Ge Junctionless Gate-all-around nFETs by selective laser annealing
5.1 Introduction..............................................................................88
5.2 Dopant recovery by second laser annealing................89
5.3 Parasitic resistance reduction with NiGe contact.......91
5.4 Device fabrication...................................................................93
5.5 Characterization of Ge JL nGAAFETs with selective
laser annealing........................................................................95
5.6 Summary....................................................................................98
5.7 References.................................................................................98

Chapter 6 Strain Response, Self-heating Effects and Low Frequency Analysis of Ge Junctionless Gate-all-around nFETs
6.1 Introduction............................................................................101
6.2 Strain response of junctionless nGAAFETs.................102
6.2.1 Tensile strain in epi-Ge on Si induced by laser
annealing.............................................................................102
6.2.2 Experimental setup and strain enhancement........104
6.2.3 Strain response and mechanism of mobility
enhancement.....................................................................106
6.3 Self-heating of junctionless nGAAFETs.......................110
6.3.1 Pulse and low temperature IV Characteristics.......110
6.3.2 Device temperature simulation...................................115
6.4 Low frequency noise of junctionless nGAAFETs......117
6.5 Summary.................................................................................119
6.6 References..............................................................................120

Chapter 7 Summary and Future Work
7.1 Summary..……………………………………………………………..123
7.2 Future work………………………………………………………….125
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