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研究生:吳彥霆
研究生(外文):Yen-Ting Wu
論文名稱:應用於生醫系統之低功耗逐漸趨近式類比至數位轉換器之設計
論文名稱(外文):Design of Low Power SAR Analog-to-Digital Converters for Biomedical System Applications
指導教授:呂學士
口試日期:2017-07-31
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:100
中文關鍵詞:逐漸趨近式類比至數位轉換器數位錯誤補償混合式單位電容次階逐漸趨近式類比至數位轉換器
外文關鍵詞:successive-approximation registeranalog-to-digital convertersdigital error correctionhybrid unit capacitorsub-ranged SAR ADC
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本篇論文提出兩個適用於逐漸趨近式類比至數位轉換器(SAR ADC)的類比及混合電路設計技術,並已經由晶片下線與量測結果驗證這些技術的實用性。
第一個技術是使用混合式的單位電容。基於先前的設計,本篇論文使用了兩種不同的單位電容,將10-bit 解析度之SAR ADC 提升至12-bit 。且由於前10-bit的電容陣列之容值大小並沒有隨之改變,因此相較於使用單一單位電容之電路架構,本技術並不會增加額外的晶片面積(小於1%),電容切換時的功耗也幾乎沒有增加。採用此技術的類比至數位轉換器在1伏特的操作電壓下,其量測之功率消耗為10.55μW,有效位元數為10.827 bits。其品質因數為29.0 fJ/conversion-step。
第二個技術是次階逐漸趨近式類比至數位轉換器。本技術在電路架構中加入了一個解析度較低的SAR ADC,用以預先得知前n個位元的粗略值,再經過一個判定切換可否省略的邏輯電路,來達到省電的效果。採用此技術的類比至數位轉換器在1伏特的操作電壓下,其模擬之功率消耗為3.683μW,有效位元數為11.818 bits。其品質因數為5.099 fJ/conversion-step。
此兩個設計都是在0.18μm 1P6M CMOS technology製作的。
This thesis presents two analog and mixed-signal circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the experimental prototypes, the presented techniques are verified.
The first technique is hybrid unit capacitors. Comparing to last work [1], the resolution bit has been enhanced by adding extra capacitor arrays with an additional smaller unit capacitor. This relevant prototype SAR ADC consumes 10.55μW at 1-V supply, and the effective number of bit (ENOB) is 10.827 bits. The resultant figure of merit (FoM) is 29.0 fJ/conversion-step by measurement results.
The second technique is applying a sub-ranged SAR ADC. By adding a 5-bit sub-ranged SAR ADC to make a pre-decision of the first 5 bits, the switching power of system could be reduced by half. This relevant prototype SAR ADC consumes 3.683μW at 1-V supply, and the ENOB is 11.818 bits. The resultant FoM is 5.099 fJ/conversion-step by simulation results.
Both of the prototypes are implemented in the 0.18μm 1P6M CMOS technology.
口試委員審定書 i
誌謝 ii
中文摘要 iii
ABSTRACT iv
CONTENTS vi
List of Figures x
List of Tables xv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 The Fundamentals of Analog-to-Digital Converters 3
2.1 Introduction 3
2.2 Performance evaluation parameters 4
2.2.1 Resolution 4
2.2.2 Offset Error and Gain Error 4
2.2.3 Differential Nonlinearity (DNL) 5
2.2.4 Integral Nonlinearity(INL) 6
2.2.5 Signal-to-Noise Ratio(SNR) 7
2.2.6 Signal-to-Noise and Distortion Ratio(SNDR) 7
2.2.7 Effective Number of Bits(ENOB) 7
2.2.8 Total Harmonic Distortion(THD) 8
2.2.9 Spurious Free Dynamic Range(SFDR) 8
2.2.10 Dynamic Range(DR) 9
2.2.11 Figure of Merit(FoM) 10
2.3 ADC Architectures 11
2.3.1 Flash ADC 11
2.3.2 Pipeline ADC 12
2.3.3 Successive Approximation Register ADC 13
2.3.4 Delta-Sigma ADC 14
2.3.5 Comparison of the ADCs 15
Chapter 3 A 1V, 12-bits, Low Power SAR ADC with Hybrid Unit Capacitors 17
3.1 Introduction 17
3.2 SAR ADC Architecture 18
3.2.1 Basic Operation of Asynchronous SAR ADC 18
3.2.2 Hybrid Capacitor Arrays 25
3.2.3 Digital Error Correction 27
3.2.4 Circuit Implementation 31
3.3 Building Blocks Implementation 35
3.3.1 Sample and Hold Circuit 35
3.3.2 Capacitor Array 42
3.3.3 Dynamic Comparator 46
3.3.4 SAR Control Logic 51
3.3.5 Digital Error Correction Logic 55
3.4 SAR ADC Simulation 57
3.4.1 Function Simulation 57
3.4.2 Dynamic Performance Simulation 58
3.4.3 Static Performance Simulation 61
3.5 Measurement Results 66
3.5.1 The PCB Design 68
3.5.2 Measurement Setup 71
3.5.3 Static Performance Measurement 73
3.5.4 Dynamic Performance Measurement 75
3.5.5 Performance Metric 76
Chapter 4 A 1V, 12-bits, Sub-Ranged SAR ADC with Hybrid Unit Capacitor 78
4.1 Introduction 78
4.2 Skipping Scenario of Switching Process 79
4.3 A Coarse ADC Applied 12-bits SAR ADC 81
4.4 SAR ADC Architecture 83
4.4.1 Circuit Implementation 83
4.4.2 SAR ADC Simulation 87
4.4.3 Measurement Results 91
Chapter 5 Conclusions 95
References 96
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