臺灣博碩士論文加值系統

鰭式場效電晶體(FinFET)具有的許多優點，使得他成為製造先進奈米積體電路的最佳選擇。此外，由於一維佈局(one-dimensional layout)相對於二維佈局(two-dimensional layout)具有較高的生產率，通常在先進奈米製程中會優先採用一維佈局。本論文提出一個自動化流程，能夠根據給定的電晶體原理圖(schematics)自動生成相對應的一維鰭式場效電晶體標準單元(standard cell)佈局，除了優化面積、線長、通孔數量及繞線軌道的數量，我們生成的佈局還考慮假性閘極與電源連繫(dummy gate power tying)並且減少使用佔於單元邊界的線(boundary wires)，使得單元間能共享假性閘極以得到緊密的標準單元擺置(placement)。據我們所知，這是第一篇提出考慮擺置效應之一維鰭式場效電晶體標準單元佈局生成的論文。我們利用線性規劃進行有效率的求解，實驗結果顯示此方法的可行性且能夠生成高質量的佈局。

Due to its many advantages, FinFET technology becomes the prominent choice of fabricating advanced nanometer integrated circuits. Moreover, due to its high manufacturability, one-dimensional (1-D) layout is often preferred to its two-dimensional counterpart in advanced technology nodes under the nanometer regime. This thesis proposes a automatic process that generates the layouts of 1-D FinFET standard cells from their transistor schematics. In addition to area, wirelength, the number of vias and routing tracks, dummy gate power tying and boundary wire occupancy minimization are considered to allow inter-cell dummy gate sharing for compact standard cell placement. To the best of our knowledge, this is the first work of layout generation for 1-D FinFET standard cells that considers inter-cell placement effects. Our formulation exploits integer linear programming (ILP) for effective computation. Experimental results show the feasibility of our approach to generate high quality layouts.

Abstract v
List of Figures ix
List of Tables xii
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Previous Works 9
3 Preliminaries 12
3.1 Middle-Of-Line (MOL) Layers . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Boundary Wire Occupancy . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Problem Formulation 15
5 ILP-Based 1-D FinFET Layout Generation 17
5.1 Transistor Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.2 Constraints for Position . . . . . . . . . . . . . . . . . . . . . 23
5.1.3 Constraints for Diffusion Sharing . . . . . . . . . . . . . . . . 27
5.2 Transistor Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.2 Constraints for CB Layer . . . . . . . . . . . . . . . . . . . . . 30
5.2.3 Constraints for Via0 . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.4 Constraints for Wire . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.5 Constraints for BWO . . . . . . . . . . . . . . . . . . . . . . . 37
5.3 Capacitive Coupling Minimization . . . . . . . . . . . . . . . . . . . 37
5.4 Pin Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6 Experimental Results 39
7 Conclusion and Future Works 46
7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Bibliography 48

[1] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, T.-J. King, J. Bokor, and C. Hu. FinFET-A self-aligned double-gate MOSFET scalable beyond 20 nm. IEEE Transactions on Electron Devices 47.12 (2000): 2320-2325.
[2] E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C.-T. Chuang, K. Bernstein, and R. Puri. Turning silicon on its edge. IEEE Circuits and Devices Magazine, 20(1):20–31, Jan.-Feb. 2004.
[3] X. Huang, W.-C. Lee, C. Ku, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu. Sub 50-nm FinFET: PMOS. In IEDM Tech. Dig., 1999, pp. 67–70
[4] B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, and C. Hu. FinFET scaling to 10 nm gate length. In Int. Electron Devices Meeting, 2002, pp. 251–254.
[5] M. Alioto. Analysis of layout density in FinFET standard cells and impact of fin technology. In Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 2010-June 2 2010
[6] Jamil Kawa. FinFET Design, Manufacturability, and Reliability. https://www.synopsys.com/designware-ip/technical-bulletin/finfet-design.html
[7] Wikipedia [Online]. https://en.wikipedia.org/wiki/Multigate_device
[8] Topaloglu, Rasit O. Design with FinFETs: Design rules, patterns, and variability. Computer-Aided Design (ICCAD), 2013 IEEE/ACM International Conference on. IEEE, 2013.
[9] K. Bhanushali and W. R. Davis. FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology. In Proc. of Int’l Symp. on Physical Design (ISPD), 2015.
[10] P. Schuddinck, M. Badaroglu, M. Stucchi, S. Demuynck, A. Hikavyy, M. Garcia-Bardon, A. Mercha, A. Mallik, T. Chiarella, S. Kubicek, R. Athimulam, N. Collaert, N. Horiguchi, I. Debusschere, A. Thean, L. Altimime, and D. Verkest. Standard cell level parasitics assessment in 20nm bpl and 14nm bff. In Electron Devices Meeting (IEDM), IEEE International, 2012, pp. 25.3.1–25.3.4.
[11] T. Kauerauf, A. Branka, G. Sorrentino, P. Roussel, S. Demuynck, K. Croes, K. Mercha, J. Bommels, Z. Tokei, and G. Groeseneken. Reliability of MOL local interconnects. InIEEE International Reliability Physics Symposium (IRPS), 2013, pp. 2F–5.
[12] K. Bhanushali. Design Rule Development for FreePDK15: An Open Source Predictive Process Design Kit for 15nm FinFET Devices. diploma thesis, North Carolina State University, Raleigh, NC 27695, May 2014.
[13] Victor Moroz. FinFET structure design and variability analysis enabled by TCAD. http://www.edn.com/design/eda-design/4398011/2/ FinFET-structure-design-and-variability-analysis-enabled-by-TCAD-, 2012. [Online; accessed 4-July-2013].
[14] T. Dillinger. Challenges for FinFET extraction. In IEEE Electronic Design Symposium, 2013.
[15] Du, Yuelin, and Martin DF Wong. Optimization of standard cell based detailed placement for 16 nm FinFET process. In Proceedings of the conference on Design, Automation & Test in Europe. European Design and Automation Association, 2014.
[16] Martins, M., Matos, J. M., Ribas, R. P., Reis, A., Schlinker, G., Rech, L., and Michelsen, J. Open cell library in 15nm FreePDK technology. In Proceedings of the 2015 Symposium on International Symposium on Physical Design. ACM, 2015. p. 171-178.
[17] P.-H. Wu, M. P.-H. Lin, T.-C. Chen, T.-Y. Ho, Y.-C. Chen, S.-R. Siao, and S.-H. Lin. 1-D Cell Generation With Printability Enhancement. IEEE Transactions on Computer-Aided Design, 32(3):419–432, March 2013.
[18] W. Ye, B. Yu, Y.-C. Ban, L. Liebmann, and D. Z. Pan. Standard cell layout regularity and pin access optimization considering middle-of-line. In GLSVLSI’15, pages 289-294. ACM, 2015.
[19] Cho, M., Pan, D. Z., Xiang, H., and Puri, R. (2006, November). Wire density driven global routing for CMP variation and timing. In Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design (pp. 487-492). ACM.
[20] P. Cremer, S. Hougardy, J. Schneider, J. Silvanus. Automatic Cell Layout in the 7nm Era. In Proceedings of the 2017 ACM on International Symposium on Physical Design. ACM, 2017.
[21] A. Hasan, D. Sharma, S. Kalra, A. Sharma, and R. Saxena. A Standard cell architecture to deal with signal integrity issues in deep submicron technologies. https://www.design-reuse.com/articles/30429/standard-cell-architecture-signal-integrity-issues.html
[22] Zhang, Hongbo, Martin DF Wong, and Kai-Yuan Chao. On process-aware 1-D standard cell design. In Proceedings of the 2010 Asia and South Pacific Design Automation Conference. IEEE Press, 2010.
[23] M. Smayling. Gridded design rules: 1-D approach enables scaling of CMOS logic. Nanochip Technol. J., vol. 6, no. 2, pp. 33–37, 2008.
[24] K. Vaidyanathan, S. H. Ng, D. Morris, N. Lafferty, L. Liebmann, M. Bender, W. Huang, K. Lai, L. Pileggi, and A. Strojwass. Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14nm node. SPIE Advanced Lithography Conference, 2012
[25] Taylor, Brian, and Larry Pileggi. Exact combinatorial optimization methods for physical design of regular logic bricks. In Proceedings of the 44th annual Design Automation Conference. ACM, 2007.
[26] A. Lu, H. J. Lu, E. J. Jang, Y. P. Lin, C. H. Hung, C. C. Chuang, and R. B. Lin. Simultaneous transistor pairing and placement for CMOS standard cells. DATE, pp. 1647-1652, Mar. 2015.
[27] Lu, H. J., Jang, E. J., Lu, A., Zhang, Y. T., Chang, Y. H., Lin, C. H., and Lin, R. B. (2016, March). Practical ILP-based routing of standard cells. In Proceedings of the 2016 Conference on Design, Automation & Test in Europe (pp. 245-248). EDA Consortium.
[28] N. Ryzhenko and S. Burns. Standard cell routing via boolean satisability. In DAC’12, pages 603-612, 2012.
[29] Golden, Bruce, S. Raghavan, and Daliborka Stanojevi. The prize-collecting generalized minimum spanning tree problem. The prize-collecting generalized minimum spanning tree problem. 14.1 (2008): 69-93.
[30] Y. Lin, B. Yu, B. Xu, and D. Z. Pan. Triple patterning aware detailed placement toward zero cross-row middle-of-line conflict. In Proc. ICCAD, 2015, pp. 396–403.
[31] (2015). Nangate 15nm Open Cell Library [Online]. Available: http://www.nangate.com
[32] Bulent Basaran. Optimal diffusion sharing in digital and analog CMOS layout. Carnegie Mellon University, Pittsburgh, PA, 1998.
[33] CPLEX Optimizer[Online]. http://www-01.ibm.com/software/commerce/optimization/cplex-optimizer/
[34] B. Yu, X. Xu, S. Roy, Y. Lin, J. Ou, and D. Z. Pan. Design for manufacturability and reliability in extreme-scaling VLSI. Science China Information Sciences, 59(6):1-23, 2016.
[35] R. Merritt. 4 Views of the Silicon Roadmap. EE Times, 2017. http://www.eetimes.com/document.asp?doc_id=1331766