臺灣博碩士論文加值系統

這篇論文的主題主要分為兩個部分，第一部分實現了一個具有背景校正供應電壓敏感度之數位鎖相迴路。利用一個全數位的校正方法加上頻率相減器去抑制供應電壓敏感度。在振盪器的供應電壓注入峰對峰值為50mV，頻率為100kHz的弦波雜訊時，量測到的峰對峰值抖動量從原本的41.48ps降低至23.15ps。量測到的方均根抖動量從原本的7.26ps 降低到3.47ps。在未注入供應電壓雜訊時，量測到的峰對峰值和方均根抖動量分別為 19.21ps 和2.71ps。此全數位鎖相迴路的面積與功耗分別為0.006mm2以及9.34mW。
第二部分實現了一個注入鎖定時脈倍頻器。透過使用延遲時間偵測器的頻率校正器，達到校正因為製程、電壓以及溫度變異造成的頻率誤差。參考突波以及時間抖動可以被顯著地降低。當注入鎖定之後，量測到的參考突波為-61.28dBc，積分範圍從10kHz到100MHz的方均根抖動量為479fs。此注入鎖定時脈倍頻器的面積與功耗分別為0.012mm2以及2.55mW。

This thesis consists of two parts. The first part implements a digital phase-locked loop (DPLL) with background supply voltage sensitivity calibration. A digital supply voltage sensitivity controller with a frequency subtractor is used to suppress the supply voltage sensitivity. With a 50mVPP, 100kHz sinusoidal supply noise tone, the calibration scheme reduces the peak-to-peak jitter from 41.48ps to 23.15ps and the rms jitter is reduced from 7.26ps to 3.47 ps. The measured peak-to-peak jitter and rms jitter without supply noise are 19.21ps and 2.71ps. Its active area is 0.006mm2 and the power consumption is 9.34mW.
The second part implements an injection-locked clock multiplier (ILCM). The ILCM is presented with a frequency calibrator (FC) using a delay time detector to calibrate the frequency error due to the process, voltage, and temperature (PVT) variations. The reference spur and timing jitter due to the PVT variations can be significantly reduced. When injection locked, the measured reference spur is -61.28dBc and the rms jitter integrated from 10kHz to 100MHz is 479fs. Its active area is 0.012mm2 and the power consumption is 2.55mW.

1. Introduction………………………………………………………… 1
1.1 Motivation…………………………………………………… 1
1.2 Overview…………………………………………………….. 3

2. A Digital Phase-Locked Loop with Background Supply Voltage Sensitivity Calibration Using a Frequency Subtractor…………... 5
2.1 Motivation…………………………………………………… 5
2.2 Supply Noise Cancellation…………………………………... 6
2.3 Circuit Description…………………………………………... 10
2.3.1 DPLL………………………………………………… 10
2.3.2 DCO and Supply Noise Cancellation………………... 15
2.3.3 Divider……………………………………………….. 17
2.3 Analysis……………………………………………………… 17
2.4 DPLL Loop Dynamics………………………………………. 21
2.5 Simulation Result..................................................................... 23
2.6 Experiment Result…………………………………………… 26
2.7 Performance Summary………………………………………. 34

3. A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector…….……….. 37
3.1 Motivation……………………………………….................... 37
3.2 Circuit Description…………………………………………... 39
3.2.1 Problem Analysis…………………..……………….. 39
3.2.2 ILCM………………………………………...……... 40
3.2.3 Pulse Generator……………………………………... 43
3.2.4 Frequency Calibrator……………………………….. 43
3.2.5 Coarse Frequency Selector…………………………. 46
3.2.6 Voltage-Controlled Oscillator………………………. 47
3.3 Linear Model Analysis……………………………………….. 48
3.4 Simulation Result……………………………………………. 51
3.5 Experiment Result…………………………………………… 53
3.5 Performance Summary………………………………………. 59

4. Conclusion and Future Work……………………………………… 61
4.1 Conclusion…………………………………………………… 61
4.2 Future Work…………………………………………………. 62

Bibliography ……………………………………………………………… 63

[1]E. Alon, J. Kim, S. Pamarti, K Chang, and M. Horowitz, “Replica Compensated Linear Regulators for Supply-Regulated Phase-Locked Loops,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413–424, Feb. 2006.

[2]T. Wu, K. Mayaram, and U. Moon, “An On-Chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 775–783, Apr. 2007.

[3]S. Y. Kao, and S. I. Liu, “A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression,” IEEE Trans Very Large Scale Integr.(VLSI) Syst., vol. 19, no. 4, pp. 592-602, April 2011.

[4]Y. C. Huang, C. F. Liang, H. S. Huang, and P. Y. Wang, “A 2.4GHz ADPLL with Digital-Regulated Supply-Noise-Insensitive and Temperature-Self-Compensated Ring DCO,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 270-271.

[5]A. Elshazly, R. Inti, W. Yin, B. Young, and P. K. Hanumolu, “A 0.4-to-3GHz Digital PLL with Supply-Noise Cancellation Using Deterministic Background Calibration,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 92-93.

[6]J. Liu, T. K. Jang, Y. Lee, J. Shin, S. Lee, T. Kim, J. Park, and H. Park, “A 0.012mm2 3.1mW Bang-Bang Digital Fractional-N PLL with a Power-Supply-Noise Cancellation Technique and a Walking-One-Phase-Selection Fractional Frequency Divider,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 268-269

[7]C. W. Yeh, C. E. Hsieh, and S. I. Liu, “A 3.2GHz Digital Phase-Locked Loop with Background Supply-Noise Cancellation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 332-333.

[8]B. Kim, S. Kundu, and Chris H. Kim, “A 0.4-1.6GHz Spur-Free Bang-Bang Digital PLL in 65nm with a D-Flip-Flop Based Frequency Subtractor Circuit,” in 2015 Symp. VLSI Circuits Dig. Tech. Papers, June 2015, pp. C140-C141.

[9]N. D. Dalt, “Linearized Analysis of a Bang-Bang Digital PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3663–3675, Dec. 2008.

[10]E.J. Pankratz, and E. Sánchez-Sinencio, “Multiloop High Power Supply Rejection Quadrature Ring Oscillator,” IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2033-2048, Sep. 2012.

[11]P.H. Hsieh, J. Maxey, and C.-K. K. Yang, “Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2488-2495, Sep. 2009.

[12]M. Mansuri, and C.-K. K. Yang, “A Low-power Adaptive Bandwidth PLL and Clock Buffer with Supply-noise Compensation,” IEEE J. Solid-State Circuits, vol.38, no. 11, pp. 1804-1812, Nov. 2003.

[13]T. Jang, S. Jeong, D. Jeon, K. D. Choo, D. Sylvester, and D. Blaauw, “A 2.5ps 0.8-to-3.2GHz Bang-Bang Phase- and Frequency-Detector-Based All-Digital PLL with Noise Self-Adjustment,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 148-149.

[14]Y. Huang and S. Liu, “A 2.4-GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 417–428, Feb. 2013.

[15]I. T. Lee, Y. J. Chen, S. I. Liu, C. P. Jou, F. L. Hsueh, and H. H. Hsieh, “A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing,” in ISSCC Dig. Tech. Papers, 2013, pp. 414–415.

[16]P. Park, J. Park, H. Park, and S. Cho, “An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS,” in ISSCC Dig. Tech. Papers, 2012, pp. 336–337.

[17]S. Leventino, G. Marucci, G. Marzin, A. Fenaroli, C. Samori, and A. Lacaita, “A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2678–2691, Nov. 2015.

[18]R. Farjad-Rad, W. Dally, H. Ng, R. Senthinathan, M. Lee, R. Rathi, and J. Poulton, “A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1804–1812, Dec. 2002.

[19]A. Elshazly, R. Inti, B. Young, and P. Hanumolu, “Clock multiplication techniques using digital multiplying delay-locked loops,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1416–1428, June 2013.

[20]Y. Lee, M. Kim, T. Seong, and J. Choi, “A low phase noise injection-locked programmable reference clock multiplier with a two-phase PVT-calibrator for ΔΣ PLLs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 3, pp. 635–644, March 2015.

[21]M. Kim, S. Choi, and J. Choi, “A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, 2015, pp. C142–C143.

[22]S. Choi, S. Yoo, and J. Choi, “A 185fs rms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 195-196.

[23]J. Shin and H. Shin, “A fast and high-precision VCO frequency calibration technique for wideband fractional-N frequency synthesizers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1573–1582, July 2010.