|
[1]E. Alon, J. Kim, S. Pamarti, K Chang, and M. Horowitz, “Replica Compensated Linear Regulators for Supply-Regulated Phase-Locked Loops,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 413–424, Feb. 2006.
[2]T. Wu, K. Mayaram, and U. Moon, “An On-Chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 775–783, Apr. 2007.
[3]S. Y. Kao, and S. I. Liu, “A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression,” IEEE Trans Very Large Scale Integr.(VLSI) Syst., vol. 19, no. 4, pp. 592-602, April 2011.
[4]Y. C. Huang, C. F. Liang, H. S. Huang, and P. Y. Wang, “A 2.4GHz ADPLL with Digital-Regulated Supply-Noise-Insensitive and Temperature-Self-Compensated Ring DCO,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 270-271.
[5]A. Elshazly, R. Inti, W. Yin, B. Young, and P. K. Hanumolu, “A 0.4-to-3GHz Digital PLL with Supply-Noise Cancellation Using Deterministic Background Calibration,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 92-93.
[6]J. Liu, T. K. Jang, Y. Lee, J. Shin, S. Lee, T. Kim, J. Park, and H. Park, “A 0.012mm2 3.1mW Bang-Bang Digital Fractional-N PLL with a Power-Supply-Noise Cancellation Technique and a Walking-One-Phase-Selection Fractional Frequency Divider,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 268-269
[7]C. W. Yeh, C. E. Hsieh, and S. I. Liu, “A 3.2GHz Digital Phase-Locked Loop with Background Supply-Noise Cancellation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 332-333.
[8]B. Kim, S. Kundu, and Chris H. Kim, “A 0.4-1.6GHz Spur-Free Bang-Bang Digital PLL in 65nm with a D-Flip-Flop Based Frequency Subtractor Circuit,” in 2015 Symp. VLSI Circuits Dig. Tech. Papers, June 2015, pp. C140-C141.
[9]N. D. Dalt, “Linearized Analysis of a Bang-Bang Digital PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3663–3675, Dec. 2008.
[10]E.J. Pankratz, and E. Sánchez-Sinencio, “Multiloop High Power Supply Rejection Quadrature Ring Oscillator,” IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2033-2048, Sep. 2012.
[11]P.H. Hsieh, J. Maxey, and C.-K. K. Yang, “Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2488-2495, Sep. 2009.
[12]M. Mansuri, and C.-K. K. Yang, “A Low-power Adaptive Bandwidth PLL and Clock Buffer with Supply-noise Compensation,” IEEE J. Solid-State Circuits, vol.38, no. 11, pp. 1804-1812, Nov. 2003.
[13]T. Jang, S. Jeong, D. Jeon, K. D. Choo, D. Sylvester, and D. Blaauw, “A 2.5ps 0.8-to-3.2GHz Bang-Bang Phase- and Frequency-Detector-Based All-Digital PLL with Noise Self-Adjustment,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 148-149.
[14]Y. Huang and S. Liu, “A 2.4-GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 417–428, Feb. 2013.
[15]I. T. Lee, Y. J. Chen, S. I. Liu, C. P. Jou, F. L. Hsueh, and H. H. Hsieh, “A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing,” in ISSCC Dig. Tech. Papers, 2013, pp. 414–415.
[16]P. Park, J. Park, H. Park, and S. Cho, “An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS,” in ISSCC Dig. Tech. Papers, 2012, pp. 336–337.
[17]S. Leventino, G. Marucci, G. Marzin, A. Fenaroli, C. Samori, and A. Lacaita, “A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2678–2691, Nov. 2015.
[18]R. Farjad-Rad, W. Dally, H. Ng, R. Senthinathan, M. Lee, R. Rathi, and J. Poulton, “A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1804–1812, Dec. 2002.
[19]A. Elshazly, R. Inti, B. Young, and P. Hanumolu, “Clock multiplication techniques using digital multiplying delay-locked loops,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1416–1428, June 2013.
[20]Y. Lee, M. Kim, T. Seong, and J. Choi, “A low phase noise injection-locked programmable reference clock multiplier with a two-phase PVT-calibrator for ΔΣ PLLs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 3, pp. 635–644, March 2015.
[21]M. Kim, S. Choi, and J. Choi, “A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, 2015, pp. C142–C143.
[22]S. Choi, S. Yoo, and J. Choi, “A 185fs rms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 195-196.
[23]J. Shin and H. Shin, “A fast and high-precision VCO frequency calibration technique for wideband fractional-N frequency synthesizers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1573–1582, July 2010.
|