跳到主要內容

臺灣博碩士論文加值系統

(18.97.14.87) 您好!臺灣時間:2025/02/09 09:43
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:陳先哲
研究生(外文):Hsien-Che Chen
論文名稱:利用非同步取樣的低功率消耗與小面積抖動偵測器
論文名稱(外文):A Low-Power and Small-Area Jitter Detector Using Asynchronous Sampling
指導教授:劉深淵
指導教授(外文):Shen-Iuan Liu
口試日期:2017-06-26
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:64
中文關鍵詞:資料抖動晶載多相位非同步取樣抖動分布直方圖
外文關鍵詞:data jitteron-chipmulti-phaseasynchronous samplingjitter distributionhistogram
相關次數:
  • 被引用被引用:0
  • 點閱點閱:300
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
隨著半導體製程往摩爾定律方向持續前進,電路設計的技術日新月異,對於有線資料傳輸速度的要求也愈來愈高。然而,當資料在高速傳輸時卻受限於通道非線性造成的劣化,其中資料轉態點在時域上的不理想性稱為時間抖動。通常會在接收端加入等化器和時脈資料回復電路以緩解資料抖動情形,因此對於接收端電路特性評估而言,抖動為一個非常重要的考量因素。本論文旨在發展一適用於有線通訊系統接收端資料抖動的偵測器。訴求於低功耗及低面積的前提下,達到以單晶片系統電路測量的方式來取代昂貴的量測儀器。應用於25億位元每秒的接收端電路,藉由所提出的低速、多相位時脈、非同步的取樣方式,從高速傳輸的資料中,可準確偵測資料抖動的分佈。此電路實現於40奈米低功耗CMOS製程,操作於1.1伏特,偵測器的功率消耗僅2.55毫瓦。 最後,電路核心所占面積為18125平方微米。
The semiconductor process development follows the direction that Moore’s law sends. The skill of the circuit design also keeps growth in recent years. High-speed wireline communication is in high demand. However, the high-speed communication may suffer from the nonlinearity of the lossy channel. The imperfections of the received data in time domain is called “timing jitter”. Usually, an equalizer and a clock/data recovery circuit are two important building blocks, which are used to improve the jitter performance of the received data. Therefore, the jitter is one of the key factors to characterize the circuits of the receiver in wireline communication. This thesis introduces a jitter detector for the received data in wireline communication. The on-chip measurement using the low-power and small-area method can substitute for the expensive automatic test equipment. The proposed work is applied in 2.5Gb/s circuit of the receiver. By using the low-speed, multi-phase, and asynchronous method, the data jitter distribution could be detected accurately from the high-speed incoming data. This circuit is implemented in 40-nm CMOS Technology. The power consumption of the jitter detector is only 2.55mW from a 1.1V supply. Finally, the core occupies an area of 18125um^2.
1 Introduction 1
1.1 Overview 1
1.2 Wireline Communication 2
1.3 Gauging Performance of Received Data 3
1.3.1 Eye Diagram 3
1.3.2 Bathtub Curve 4
1.4 Brief Summary 5

2 Analysis of the Timing Jitter 7
2.1 Overview 7
2.2 Composition of Timing Jitter 8
2.3 Random Jitter and Sinusoidal Jitter 9
2.3.1 Random Jitter 9
2.3.2 Sinusoidal Jitter 10
2.4 Brief Summary 12

3 A Low-Power and Small-Area Jitter Detector Using Asynchronous Sampling 13
3.1 Motivation 14
3.2 Reconstruction of Jitter distribution 15
3.2.1 High-Speed Multi-Phase and Synchronous Sampling 16
3.2.2 Low-Speed Multi-Phase and Asynchronous Sampling 17
3.2.3 Proposed Low-Speed Sampling With Reconstructing Distribution 18
3.3 Performance Analysis 20
3.3.1 Data with Gaussian Jitter and Ideal Sampling Clock 20
3.3.2 Data with Gaussian Jitter and Real Sampling Clock 25
3.3.3 Data with Sinusoidal Jitter and Ideal Sampling Clock 27
3.3.4 Data with Sinusoidal Jitter and Real Sampling Clock 29
3.4 Circuit Description 31
3.4.1 Data Transition Detection and Number of Sampling Clocks 31
3.4.2 Delay-Locked Loop 32
3.4.3 Jitter Detector 34
3.4.4 Transistor-level Simulation by HSPICE 37
3.5 Experimental Results 39
3.6 Conclusion 43

4 Clock and Data Recovery Using Charge-Steering Logic Circuits 45
4.1 Motivation 46
4.2 Charge-Steering Logic Circuits 47
4.2.1 Charge-Steering Latch 47
4.2.2 Charge-Steering Flip-Flop 49
4.3 Design of 10-Gb/s CDR /De-multiplexer 50
4.3.1 Half-rate Linear Phase Detector 51
4.3.2 LC VCO and Loop Filter 53
4.3.3 Divider, De-multiplexer, and RZ-to-NRZ Converter 55
4.4 Experimental Results 56
4.4.1 Measurements of Eye Diagram and Clock Spectrum 56
4.4.2 Measurements of Jitter Transfer and Jitter Tolerance 58
4.5 Conclusion 59

5 Conclusion and Future Work 61
5.1 Conclusion 62
5.2 Future Work 62

Bibliography 63
[1]B. Analui, A. Rylyakov, S. Rylov, M. Meghelli, and A Hajimiri, “A 10-Gb/s Two-dimensional eye-opening monitor in 0.13-μm standard CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2689-2699, Dec. 2005.
[2]T. Suttorp and U. Langmann, “ A 10-Gb/s CMOS serial-link receiver using eye-opening monitoring for adaptive equalization and for clock and data recovery,” IEEE Custom Integrated Circuits Conference (CICC), pp. 277-280, Sep. 2007.
[3]D. H. Kwon, Y. S. Park, and W. Y. Choi, “A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 62, no. 6, pp. 1472-1480, June 2015.
[4]T. Ellermeyer, U. Langmann, B. Wedding, and W. Pöhlmann, “A 10-Gb/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1958-1963, Dec. 2000.
[5]F. Gerfers, G. W. Besten, P. V. Petkov, J. E. Conder, and A. J. Koellmann, “A 0.2–2 Gb/s 6x OSR receiver using a digitally self-adaptive equalizer,” IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1436-1448, June 2008.
[6]J. W. Lee, C. H. Bae, Y. Kim, and C. Yoo, “Measurement of intersymbol interference jitter by fractional oversampling for adaptive equalization,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 59, no. 11, pp. 716-720, Nov. 2012.
[7]H. S. Won, K. S. Han, S. E. Lee, J. H. Park, and H. M. Bae, “An on-chip sigma-tracking eye-opening monitor for BER-optimal adaptive equalization,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Sep. 2015.
[8]C. K. Seong, J. S. Rhim, and W. Y. Choi, “A 10-Gb/s adaptive look-ahead decision feedback equalizer with an eye-opening monitor,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 59, no. 4, pp. 209-213, Apr. 2012.
[9]W. S. Kim, C. K. Seong, and W. Y. Choi, “A 5.4-Gbit/s adaptive continuous-time linear equalizer using asynchronous undersampling histograms,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 59, no. 9, pp. 553-557, Sep. 2012.
[10]B. Dehlaghi, S. Magierowski, and L. Belostotski, “A 12.5-Gb/s on-chip oscilloscope to measure eye diagrams and jitter histograms of high-speed signals,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 5, pp. 1127-1137, May 2014.
[11]Application Note 1448-1, “Measuring jitter in digital systems,” in Agilent Technologies, Inc., pp. 2-6, June 2003.
[12]M. P. Li, “Jitter, noise, and signal integrity at high-speed,” Prentice Hall, pp. 92-93, Nov. 2007.
[13]R. Stephens, Agilent Technical Note White Paper, “Jitter analysis: the dual-dirac model, RJ/DJ, and Q-scale,” in Agilent Technologies, Inc., pp. 9, Dec. 2004.
[14]Application Note AN-815, “Understanding jitter units,” in Integrated Device Technology, Inc., pp. 6, Mar. 2014.
[15]H. H. Chang, J. W. Lin, C. Y. Yang, and S. I. Liu, “A wide-range delay-locked loop with a fixed latency of one clock cycle,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1021-1027, Aug. 2002.
[16]U. Karthaus and S. Schabel, “Write pulse generator for 16x DVD recording with symmetric CMOS inverter ring oscillator,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2286-2295, Nov. 2005.
[17]S. H. Lee, M. S. Hwang, Y. Choi, S. Kim, Y. Moon, B.J. Lee, D. K. Jeong, W. Kim, Y. J. Park, and G. Ahn, “A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1822-1830, Dec. 2002.
[18]B. Razavi, “Charge Steering: A Low-Power Design Paradigm,” IEEE Custom Integr. Circuits Conf., Sept. 2013, pp. 1-8.
[19]J. W. Jung and B. Razavi, “A 25-Gb/s 5-mW CMOS CDR/Deserializer,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 684-697, Mar 2013.
[20]J. Savoj and B. Razavi, “A 10-Gb/s clock and data recovery circuit with a half-rate linear phase detector, ” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 761-768, May 2001.
[21]C. F. Liao and S. I. Liu, “A 40 Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery,” IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2492-2502, Nov. 2008.
[22]B. Razavi, “ RF Microelectronics,” Pearson, 2012.
[23]B. Razavi, “Design of integrated circuits for optical communications,” McGraw-Hill, 2003.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top