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研究生:劉芳瑜
研究生(外文):Fang-Yu Liu
論文名稱:利用搜尋空間分割平行測試圖樣產生技術增進橋接故障偵測覆蓋率
論文名稱(外文):Improving Bridging Fault Coverage by Parallel Search Space Partitioning ATPG
指導教授:黃俊郎黃俊郎引用關係
指導教授(外文):Jiun-Lang Huang
口試日期:2017-07-24
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:40
中文關鍵詞:積體電路測試橋接故障測試圖樣產生技術搜尋空間分割平行可靠性平行化程式設計
外文關鍵詞:VLSI testingbridging faultATPGsearch space partitioningreliabilityparallel programming
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由於IC的製成尺寸縮小和設計複雜度增加,簡單的錯誤模型(fault model)已經無法達到足夠的缺陷(defect)偵測率。
為了更準確增加偵測到缺陷的機會,本篇論文利用實體設計(physical design)資訊,找出實際可能發生橋接故障(bridging fault)的位置,並針對橋接故障產生偵測圖樣。
本篇論文中提出了一個利用平行化搜尋空間分割(search space partitioning)增進橋接故障偵測機率的測試圖樣產生技術。主要是利用在平行化搜尋空間分割時,加入需要偵測的橋接故障,並在產生的多組測試圖樣中,挑選能提升偵測橋接故障比例最高的測試圖樣。
本論文提出的方法在ISCAS89和ITC99測試電路上進行實驗,實驗結果顯示,與N次測試自動畫圖樣產生流程相比,本論文更能實際提升偵測到橋接故障的機會,不會產生過多的測試圖樣。
Because of the shrinking feature sizes of modern IC’s (Integrated Circuit) and the in-creasing design complexity, single stuck-at fault model is no longer sufficient to achieve the desired defect coverage.
To increase the defect coverage, in this thesis, we utilize the physical design in-formation to identify the locations where bridging faults are more likely to occur. Then, test patterns are generated to target these bridging faults.
In this thesis, an ATPG (Automatic Test Pattern Generation) that improves bridg-ing fault coverage by parallel search space partitioning is proposed. Once the stuck-at fault test cubes generated by search space partitioning are available, it continues mak-ing input assignments to activate bridging faults. From the generated test cubes, the one that increases the bridging fault coverage the most is selected.
The proposed techniques are validated using ISCAS89 (International Symposium on Circuits and Systems) and ITC99 benchmark circuits. The experimental results show that the proposed techniques can achieve better bridging fault coverage and with acceptable test inflation.
CONTENTS
口試委員會審定書 #
誌謝 i
中文摘要 ii
ABSTRACT iii
CONTENTS iv
LIST OF FIGURES vii
LIST OF TABLES ix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Related Work 1
1.3 Organization of the Thesis 3
Chapter 2 Preliminaries 4
2.1 Bridging Fault Model 4
2.1.1 Types of Bridging Faults 4
2.1.2 The Inadequacy of Covering Bridging Defects by Stuck-At Fault Model 4
2.2 Multiple-detection ATPG 5
2.2.1 Multiple-detection ATPG Flow 5
2.2.2 Multiple-detection ATPG Metrics 6
2.2.3 Advantage and Disadvantage of Multiple-detection ATPG 7
2.3 Embedded Multi-detect ATPG 8
2.3.1 Embedded Multi-detect ATPG Flow 8
2.3.2 Advantage and Disadvantage of Embedded Multi-detect ATPG 9
2.4 Search Space Partitioning ATPG 9
2.4.1 Splitting the search space 9
2.4.2 Advantage of Search Space Partitioning ATPG 10
Chapter 3 Proposed Improving Bridging Fault Coverage by Parallel Search Space Partitioning ATPG 11
3.1 The Objective of the Proposed Technique 11
3.2 Overall Strategy 11
3.3 RC-extraction 12
3.3.1 Layout Information 12
3.3.2 The Analysis of Bridging Faults 12
3.4 Build the Bridging Fault List 13
3.5 Bridging Fault ATPG 14
3.5.1 Bridging Fault ATPG Flowchart 14
3.5.2 Primary Fault Selection 15
3.5.3 Search-space Partitioning ATPG 15
3.5.4 Activate Bridge Fault 16
3.5.5 Test Cube Selection 17
3.5.6 Test Cube Reuse 17
3.5.7 Secondary Fault Selection 18
3.5.8 Fault Dropping 18
3.5.9 The Detail of the Master Thread and the Slave Threads 19
Chapter 4 Experiment Result 20
4.1 Bridging Fault Coverage (BFC) 20
4.1.1 The Definition of Bridging Fault Coverage 20
4.1.2 The Analysis of Bridging Fault Coverage 20
4.2 Previous Works Setup 21
4.3 Compare Single-detect ATPG with BF-ATPG 22
4.4 Compare Embedded 8-detect ATPG with BF-ATPG 26
4.5 Compare 8-detect ATPG with BF-ATPG 30
Chapter 5 Conclusion 38
REFERENCE 39
[1]Erik Jan Marinissen and Sandeep K. Goel. ITC''06 Panel Report: Zero Defects, Mission Impossible? in IEEE Design & Test of Computers, 24(1):94-95, 2007.
[2]X. Lin et al., "Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects," in Asian Test Symposium, pp. 139-146, 2006.
[3]A. F. Lin, K. Y. Liao, K. Y. Chiang and J. C. M. Li, "TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects," in VLSI Design, Au-tomation and Test, pp. 1-4, 2015.
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[7]A. Czutro, M. Sauer, T. Schubert, I. Polian and B. Becker, "SAT-ATPG using preferences for improved detection of complex defect mechanisms," in IEEE VLSI Test Symposium, pp. 170-175, 2012.
[8]D. Erb, K. Scheibler, M. Sauer and B. Becker, "Efficient SMT-based ATPG for interconnect open defects," in Design, Automation & Test in Europe Conference & Exhibition, pp. 1-6, 2014.
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[12]J. Geuzebroek, E. J. Marinissen, A. Majhi, A. Glowatz and F. Hapke, "Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects," in In-ternational Test Conference, pp. 1-10, 2007.
[13]V. Krishnaswamy, A. B. Ma and P. Vishakantaiah, "A study of bridging defect probabilities on a Pentium (TM) 4 CPU," in International Test Conference, pp. 688-695, 2001.
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