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研究生:周代恩
研究生(外文):Dai-En Jhou
論文名稱:適用於LC振盪器之倍數延遲鎖定迴路架構的分數型頻率合成器
論文名稱(外文):A Fractional-N Frequency Synthesizer with an LC-VCO-based Multiplying Delay-Locked Loop Architecture
指導教授:李泰成
指導教授(外文):Tai-Cheng Lee
口試委員:鄭國興林宗賢劉深淵
口試委員(外文):Kuo-Hsing ChengTsung-Hsien LinShen-Iuan Liu
口試日期:2017-04-06
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:55
中文關鍵詞:分數型頻率合成器倍數延遲鎖定迴路LC振盪器再量化三角積分調變器數位時間轉換器
外文關鍵詞:fractional-N frequency synthesizersmultiplying delay-locked loop (MDLL)LC-VCOre-quantized delta-sigma modulator (DSM)digital-to-time converter (DTC)
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本論文呈獻一個操作於5.12-GHz以LC振盪器之倍數延遲鎖定迴路為架構的分數型頻率合成器,此架構在長除數為128的狀況下仍可達到低雜訊效能。運用所提出的多工器在LC振盪器中,可將迴路頻寬由3-MHz增加至15-MHz (將近0.4倍參考頻率)且有抑制其中閃爍雜訊的效果。此外,此架構與再量化三角積分調變器的結合更可減少由於數位時間轉換器中的增益誤差所產生的突波量值和頻寬內雜訊。
這個提出的架構被實現於40nm CMOS工藝上,其主要面積為0.2平方毫米。在0.9伏特的電源供應下,其操作在5.12-GHz的抖動量 (被積分範圍從10-kHz到30-MHz)為177 fsrms (整數型)和326 fsrms (分數型),各自對應的功耗為1.81 mW和2.38mW,即便使用一個較低的40-MHz參考時脈。所提出的分數型頻率合成器在ㄧ個長除數頻率為128的狀況下,其質量因數 (figure-of-merit)最佳可達-252.5 dB (整數型)和-246 dB (分數型)。
This thesis presents a 5.12-GHz fractional-N frequency synthesizer with an LC-VCO-based multiplying delay-locked loop (MDLL) architecture which can achieve lower noise performance even with a large frequency multiplication factor (N) of 128. By employing the proposed MUXs in the LC-VCO, it increases the loop bandwidth (BW) from 3-MHz to 15-MHz (nearly 0.4fREF) as well as flicker noise suppression. Moreover, the re-quantized delta-sigma modulator (DSM) is combined with the prototype in order to reduce spurious tones and in-band noise, which come from the gain error of the digital-to-time converter (DTC).
The proposed prototype has been fabricated in a 40 nm CMOS technology and occupies an area of 0.2 mm2. The integrated jitters, integrated from 10-kHz to 30-MHz, are 177 fsrms (integer-N) and 326 fsrms (fractional-N) with power consumption of 1.81 mW and 2.38 mW from a 0.9 V supply at 5.12-GHz respectively even with a lower reference clock of 40MHz. The figure-of-merit (FoMJ) of the proposed fractional-N frequency synthesizer can be as good as -252.5 dB (integer-N) and -246 dB (fractional-N) with a large frequency multiplication factor (N) of 128.
口試委員審定書 (中/英)
誌謝
摘要 i
Abstract ii
Contents iii
List of Figures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Motivation and Research Goals 1
1.2 Thesis Organization 3
Chapter 2 Basic Concepts 4
2.1 PLL-based Frequency Synthesizers 4
2.1.1 Integer-N PLL 4
2.1.2 Fractional-N PLL 5
2.1.3 Linear Model of Traditional PLL 6
2.2 Review of the Multiphase Compensation Method 12
2.3 Review of the VCO realignment techniques 14
2.3.1 Multiplying Delay-Locked Loop (MDLL) 15
2.3.2 Sub-harmonic Injection-Locked PLL (SIPLL) 16
2.3.3 Linear Model of the VCO Realignment 17
2.4 Summary 19
Chapter 3 A 5.12-GHz Fractional-N Frequency Synthesizer with an LC-VCO-based MDLL 20
3.1 Introduction 20
3.2 The Proposed Fractional-N Frequency Synthesizer 21
3.2.1 Block Diagram 21
3.2.2 Analysis of the Realignment Factor (β) 22
3.3 Proposed LC-VCO-based MDLL 24
3.3.1 Challenge of the LC-VCO-based MDLL 24
3.3.2 Related Suppression of Flicker Noise in LC-VCO Technique 25
3.3.3 Proposed LC-VCO-based MDLL 27
3.4 Proposed MDLL in Fractional-N mode 29
3.4.1 Challenge of the Fractional-N Frequency Synthesizer 29
3.4.2 The Operation of Fractional-N Mode 30
3.4.3 Analysis of the  modulator in the fractional-N mode 31
3.5 Other Circuit Implementation 34
3.5.1 DTC 34
3.5.2 REF&SEL Generator 34
3.5.3 Traditional PLL 35
3.6 Behavior Simulation 37
3.7 Summary 38
Chapter 4 Experimental Results 39
4.1 Measurement Environment 39
4.2 Chip Configuration 41
4.3 Experimental Results 42
4.4 Comparison and Performance Summary 46
Chapter 5 Conclusion 49
5.1 Thesis Summary 49
5.2 Future Works 50
Bibliography 51
Biography 54
Publication List 55
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[12]B. M. Helal, M. Z. Straayer, G.-Y. Wei, and M. H. Perrott, “A highly digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 855–863, Apr. 2008.
[13]B. Razavi, “A study of injection locking and pulling in oscillators,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415-1424, Sep. 2004.
[14]J. Lee and H. Wang, “Study of subharmonically injection-locked PLLs,” IEEE J. Solid-State Circuits, vol. 44, pp. 1539-1553, May 2009.
[15]Y.-C. Huang and S.-I. Liu, “A 2.4-GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 417–428, Feb. 2013.
[16]I.-T. Lee, K.-H. Zeng, S.-I. Liu, “A 4.8-GHz dividerless subharmonically injection-Locked all-digital PLL with a FOM of -252.5 dB,” IEEE Trans. Circuits Syst. II, vol. 60, pp. 547-551, Jul. 2013.
[17]A. Elkholy, et al., "A 6.75-to-8.25GHz,250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 192-193.
[18]F. Pepe, A. Bonfanti, S. Levantino, C. Samori, and A. L. Lacaita,“Suppression of flicker noise up-conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz band,” IEEE J. Solid-State Circuits, vol. 48, no. 10, pp. 2375–2389, Oct. 2013.
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