臺灣博碩士論文加值系統

我們使用新思科技的Sentaurus TCAD軟體模擬砷化銦-矽異質接面環繞式閘極奈米線穿隧式場效應電晶體之電特性。結果顯示與矽同質接面相比砷化銦-矽異質接面有更大的導通電流，而與單閘極結構相比環繞式閘極結構有更好的次臨限斜率。原因為砷化銦-矽異質接面的穿隧能障比矽同質接面小而環繞式閘極結構的閘極控制力比單閘極結構好。此外，因為穿隧現象主要發生在奈米線表面所以奈米線的直徑對電晶體的特性影響不大。為了改善次臨限斜率特性，我們提出矽袖珍結構。此結構能夠藉由矽到矽的穿隧現象降低次臨限斜率。而為了提高導通電流，我們提出內核外殼結構。此結構能夠藉由增加發生穿隧現象的面積提高導通電流。不過因為側向的穿隧能障會隨著內核長度增加而變大，所以導通電流不與內核長度成正比。

The electrical characteristics of InAs-Si heterojunction GAA NW TFET are simulated using Sentaurus TCAD produced by Synopsys. Results show that InAs-Si heterojunction can enlarge the on-state current compared with Si homo-junction and GAA structure can improve the subthreshold slope compared with single gate structure. The reasons are that the tunnel barrier width of InAs-Si heterojunction is smaller than Si homo-junction and the GAA structure has better gate control than single gate structure. Besides, the diameter of nanowire scarcely affects the performance of device due to the tunneling mainly occurring at nanowire surface. To further improve the subthreshold slope, we introduce Si pocket structure. This structure can further decrease the subthreshold slope by Si to Si tunneling mechanism. On the other hand, to further increase the on-state current, we introduce core shell structure. This structure can further increase on-state current because it enlarges the tunnel area. However, the on-state current does not increase proportional to the core length due to the tunnel barrier width in the direction across channel increases as the core length increasing.

Content
中文摘要…………………………………………………………………………………I
Abstract………………………………………………………………………………….II
Content………………………………………………………………………………….III
List of Figure…………………………………………………………………………...VI
List of Table………………………………………………………………………....XXII
Chapter 1 Introduction……………………………………………………………….......1
1.1 Background……………………………………………………………….…….....1
1.2 Band-to-band Tunneling……………………………...……………………….......3
1.3 Natural Length……………………………………………………………….……6
1.4 Motivation………………………………………………………………………...7
1.5 Thesis Organization……………………………………………………………….8
Chapter 2 Simulation Procedure and Convergence Test…………………………...........9
2.1 Sentaurus TCAD………………………….……………………………….............9
2.2 Sentaurus TCAD Workflow……………………………………………...………..9
2.3 Simulation Procedure…………………………...….……………………………12
2.4 Convergence Test……………………………………………………..................13
2.5 Simulation Divergence…………………………….……………………….........18
2.6 Symmetry of Result……………………………………………………………...20
2.7 Self-consistency………………………………………………………………….24
2.8 Time Consumption and Memory Usage…………………………………………24
2.9 Computer Specifications…………………………………………………………26
Chapter 3 InAs-Si Heterojunction GAA NW TFET…………………………..………..27
3.1 N-type InAs Nanowires on P-type Si Substrate…………………………............27
3.2 Fabrication of Device…………………………………………………................31
3.3 Device Structure and Simulation Parameters…………………………................32
3.4 Optimization…………………………………………………..............................34
3.5 Effect of NW Diameter…………………………………………………………..49
3.6 Effects of InAs-Si Heterojunction and GAA Structure………………………….54
Chapter 4 Si Pocket Structure……………………………………..………………........68
4.1 Device Structure and Simulation Parameters…………………………................68
4.2 Effect of Si Pocket Length…………………………………………………….....69
4.3 Results and Discussion……………………………………..................................72
Chapter 5 Core Shell Structure…………………………………………………………84
5.1 3D Simulation and 2D Simulation……………………………………..…….......84
5.2 Device Structure and Simulation Parameters…………………………...……….93
5.3 Effect of Core Diameter…………………………………………………….........96
5.4 Effect of Core Length…………………………………………………………..103
5.5 InAs Core Shell Structure………………………………………...……….........114
Chapter 6 Conclusion……………………………………………................................127
Bibliography………………………………..................................................................128

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