臺灣博碩士論文加值系統

聲音，是人接觸外界的一個媒介。人耳作為一個接受器，能接收20至20000赫茲的頻率，且有非常高的敏感度。隨著科技日新月異的進步，儲存裝置的空間成指數性的成長，人們對於聲音解析度的需求也愈發的旺盛，高解析度的類比數位轉換器及數位類比轉換器更是不可或缺。近年，手持式裝置及穿戴式裝置的蓬勃發展，以及環保意識的興起，低功耗也成為了設計電路的考量。快速連續漸進暫存器式類比數位轉換器雖然具有中速與低功耗的優點，然而其解析度會受到電容大小的限制，當需求超過12位元時，其功耗與設計難度會大幅的增加。而音頻信號頻率小於兩萬赫茲，符合三角積分式類比數位轉換器操作頻率低的特性。三角積分式類比數位轉換器可透過雜訊形塑的方式降低高頻的量化雜訊；同時，藉由高於訊號頻率數倍的取樣頻率，可以降低頻帶內的雜訊。透過這兩種效果，三角積分式類比數位轉換器可以輕易達到高解析度的效果。
本篇論文提出應用於音頻的低功耗三角積分類比數位轉換器的設計方法，包括整體系統規格設計、前端MATLAB程式模擬，並詳細分析各種非理想效應對於效能的影響，同時使用模擬來作驗證。電路使用UMC 0.18um的製程技術來完成。設計上使用CIFF的三階架構，以減少能量的消耗。設計在布局後的解析度，成功達到了高解析度的目標。

The voice is a medium that touches the outside world. The human ear as a receiver, can receive 20 to 20000 Hz frequency, and has a very high sensitivity. With the rapid progress of science and technology, the storage device space into the exponential growth, people demand for sound resolution is also increasingly strong, high-resolution analog digital converter and digital analog converter is indispensable. In recent years, the vigorous development of handheld devices and wearable devices, as well as the rise of environmental awareness, low power consumption has become a design consideration. Successive approximation register analog-to-digital converter has the advantages of medium speed and low power consumption, but its resolution will be limited by the size of the capacitor, when the demand exceeds 12 bits, the power consumption will significantly increase and design will be difficult. While the audio signal frequency is less than twenty thousand hertz, which is match in delta-sigma analog-to-digital converter operating frequency characteristics. Delta-sigma analog-to-digital converters can reduce the high-frequency quantization noise through noise shaping. At the same time, the noise in-band can be reduced by sampling the frequency higher than the signal frequency several times. Through these two effects, delta-sigma analog-to-digital converter can easily achieve high-resolution.
This thesis presents a design method for low-power delta-sigma analog-to-digital converters for audio applications, including overall system specification design, MATLAB program simulation, and detailed analysis of the effects of various non-ideal effects on performance, while using simulation for verification. The circuit is done using UMC 0.18um process technology. We use 3rd-order CIFF architecture to reduce energy consumption. The first design after the layout of the resolution, successfully reached the high-resolution goal.

口試委員會審定書 i
誌謝 ii
中文摘要 iii
ABSTRACT iv
CONTENTS vi
LIST OF FIGURES ix
LIST OF TABLES xiii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization 2
Chapter 2 Basic Background Information 3
2.1 Fundamental of Analog-to-Digital Converters 3
2.2 Types of ADCs 5
2.2.1 Nyquist Rate ADCs 6
2.2.2 Oversampling ADCs 7
2.3 Quantization Noise 9
2.4 Oversampling 11
2.5 Noise Shaping 13
2.5.1 First-Order Noise Shaping 15
2.5.2 Second-Order Noise Shaping 16
2.5.3 Nth-Order Noise Shaping 18
2.6 Overall Architecture 19
2.6.1 Loop Filter 19
2.6.2 Quantizer 23
2.6.3 Digital-to-Analog Converter 26
2.7 Continuous-Time Delta-Sigma Modulator 27
2.7.1 Z-Domain to S-Domain Transformation 28
2.7.2 DAC Waveform and Clock Jitter 29
2.7.3 Metastability and Excess Loop Delay 32
2.8 Summary 33
Chapter 3 Continuous-Time DSM Model Analysis and Simulation 34
3.1 Design Flow and Consideration 34
3.2 MATLAB Simulation 36
3.2.1 Loop Filter Non-idealities Simulation in MATLAB 39
3.2.2 DAC Non-idealities Simulation 42
3.3 Cadence Simulation 44
3.3.1 Transient Simulation 46
3.3.2 Device Noise Simulation 49
3.4 Conclusion 50
Chapter 4 Continuous-Time Delta-Sigma Modulator Implementation 51
4.1 Loop Filter 51
4.1.1 OP Design 52
4.1.2 Resistors and Capacitors Value in Signal Path 56
4.2 SAR ADC 57
4.3 Dynamic Element Matching (DEM) 59
4.4 DAC 59
4.5 Calibration Circuit 62
4.6 Whole System Simulation Result 65
4.6.1 Pre-Simulation 65
4.6.2 Simulation with Real Resistors and Capacitors 65
4.6.3 Simulation with Device Noise 66
Chapter 5 Conclusion 71
References 73

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