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研究生:王律文
研究生(外文):Lu-Wen Wang
論文名稱:運用連續波都卜勒之高效能源利用超音波接收端
論文名稱(外文):Power-Efficient Ultrasound Receiver in Continuous Wave Doppler Mode
指導教授:呂良鴻
口試委員:黃俊郎林宗賢郭建男
口試日期:2017-03-15
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:英文
論文頁數:143
中文關鍵詞:超音波接收端連續波都卜勒類比前端電路互補式金屬氧化物半導體
外文關鍵詞:ultrasound receivercontinuous wave Doppleranalog front-endCMOS
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臨床應用中,都卜勒超音波技術廣泛地被應用在生理循環系統的探索和心臟血管動力學的評估中。藉由解析超音波反彈波形的振幅和頻率飄移,可以知悉血管內的血液流速及方向資訊。近年來隨著醫學技術的進步,對高性能、攜帶型超音波成像系統的需求日益漸增。
一般超音波接收端商品包含了兩路接收機制,時間增益補償模式和連續波都卜勒模式。這兩路機制共用了接收系統最前端的低雜訊放大器,然而礙於性能的嚴格限制,只有時間增益補償模式的系統電路有完整地整合在單晶片商品中。基於互補式金屬氧化物半導體本身的優勢和特性,本論文使用該製程實作了一個低成本、高效能源利用並高度整合的連續波都卜勒超音波接收系統,包含了多通道的低雜訊放大器、混頻器(相移器)、加法器、濾波器、音頻類比數位轉換器和本地震盪器的方波產生電路,除低雜訊放大器和方波產生電路外其餘電路皆包含了同相通道和正交通道。
電路設計上,低雜訊放大器採用高輸出擺幅架構並加入了線性度優化技巧,降低了總諧波失真和交互調變失真。混頻器結合了被動式混頻器的優點和負回授運算放大器的虛短路特性,降低了在訊號向下轉換和相移的過程中對動態範圍的減損。另外,在加法器和濾波器所使用的全差動運算放大器電路中,展示了ㄧ種可以穩定共模電壓回授迴路的相位邊際的技巧。電路佈局方面,在循續漸近式的音頻類比數位轉換器裡根據了既有的三明治單位電容畫法,提出了ㄧ個新型的混合式三明治單位電容畫法和ㄧ些與之相對應的電容陣列的走線及佈局技巧,有效地控制了寄生電容的產生和其對轉換器的線性度的影響。最後,在系統各區塊處許多差動電路的輸出點上皆應用了數位的方式校正了偏移電壓。除了預防各電路操作在錯誤的偏壓點上進而降低整體系統的動態範圍,也避免因為採用類比校正方式而需要大量的片外電容導致成本增加。
In the clinical applications, Doppler ultrasound is widely used to understand the circulation physiology and the evaluation of cardiovascular hemodynamics. By means of analyzing the amplitude and the frequency shift (Doppler shift) of the received ultrasound signals, it is possible to acquire the information about flow rate and flow direction of blood. Recently, the demand for portable ultrasound imaging system with high performance becomes larger as the medical technology is advanced.
In general, commercial products of ultrasound receiver include two receiving mechanisms, time-gain-compensation (TGC) mode and continuous-wave (CW) Doppler mode. These two operation modes have a shared LNA at the circuit input, however, only the circuit system of TGC mode is fully integrated on single chip due to the strict limit of performance. Based on the advantages and the characteristics of a complementary metal-oxide-semiconductor (CMOS) process, a low cost, power-efficient and fully integrated ultrasound receiver in continuous-wave Doppler (CWD) mode is presented in this thesis. The proposed CWD receiver is composed of multi-channel LNAs, mixers, summing amplifier, anti-aliasing filter, audio-frequency analog-to-digital converter (ADC) and clocking circuit for local oscillator (LO) generation. Except the clocking circuit and LNAs, all the circuit blocks include in-phase and quadrature (I/Q) channels.
In the circuit designs, the proposed LNA adopts a high-out-swing topology and a linearity-improving skill to lower the total harmonic distortion (THD) and the two-tone third-order intermodulation distortion (IMD3). Combining advantages of the passive mixer and the characteristic of virtual short in an operational amplifier (Op-amp) based inverting amplifier, the mixers used in this design reduce the degradation of dynamic range (DR) during the beamforming and the down-conversion of amplified signals. Besides, a skill of improving the phase margin of common-mode feedback (CMFB) loop in both the summing amplifier and filter which are based on fully differential op-amps is demonstrated. Based on an existing layout skill of using the sandwich capacitor as a unit capacitor in a capacitive digital-to-analog (CDAC) array of successive approximation (SAR) ADC, a hybrid sandwich capacitor is proposed to increase the capacitance of unit capacitor occupying an equal area. In addition, the corresponding layout floor plan and wiring skill inside CDAC is also depicted to effectively control the generation of parasitic capacitors and prevent the linearity of converter from deterioration because of them. Finally, offset-calibrating circuits adopting a digital method are used to remove offsets at outputs of differential circuits. It can not only keep from a decrease in dynamic range (DR) of entire system due to the wrong operation region of transistors but also avoid using lots of off-chip capacitors which is needed in an analog method and would increase the cost.
口試委員會審定書 i
誌謝 v
摘要 vii
Abstract ix
Contents xi
List of Figures xv
List of Tables xxiii
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.2 Thesis Organization 5
Chapter 2 Overview of Ultrasound Receiver in Continuous Wave Doppler Mode 7
2.1 Fundamentals of Continuous Wave Doppler Ultrasound 7
Doppler Ultrasound 7
The Doppler Principle 7
Blood Flow Hemodynamics 8
Continuous Wave Doppler (CWD) 9
CWD Ultrasound 9
Basis of Operation 11
Discrimination of the Direction of Flow 12
2.2 Operation of Ultrasound System in CWD mode 14
2.3 Design Challenges of CWD in Compact Ultrasound-Imaging Equipment 15
2.3.1 Delay-Line-Based CWD Beamformer 16
2.3.2 Mixer-Based CWD Beamformer 18
2.4 Comparison between Commercial Products and the Proposed Ultrasound Receiver in CW Mode 19
2.5 Design Specification of the Proposed CWD Receiver 23
2.5.1 Design Parameters of LNA 24
2.5.2 Design Parameters of ADC 24
2.5.3 Design Parameters of Gain of Summing Amplifier 25
Chapter 3 8-Channel In-Phase & Quadrature Local Oscillator Generator 29
3.1 Introduction 29
3.2 Proposed Architecture 30
3.3 Circuit Implementation of the Proposed LO Generator 31
3.3.1 16-Phase Clock Generator 31
3.3.2 Switch Array of Phase Steering 31
3.3.3 Clock Resamplers & Digital Buffers 33
3.3.4 40-bit serial-to-parallel converter 33
3.4 Simulation Results 35
3.5 Conclusion 36
Chapter 4 Ultrasound Beamformer 37
4.1 Introduction 37
4.2 Circuit Implementation of Ultrasound Beamformer 38
4.2.1 LNA with linearity improvement &DC calibration 38
4.2.2 CWD Mixer/Beamformer 46
4.2.3 Summing Amplifier 49
4.2.4 Anti-Aliasing Filter 58
4.3 Experimental Results 63
4.3.1 LNA 63
4.3.2 Anti-Aliasing Filter 67
4.4 Conclusion 68
Chapter 5 10-Bit Successive Approximation Register Analog/Digital Converter 69
5.1 Introduction 69
5.2 Proposed Architecture 69
5.3 Circuit Implementation of the 10-Bit SAR ADC 72
5.3.1 Bootstrapping Switch 72
5.3.2 Successive Approximation Register 75
5.3.3 Comparator with DC Offset Calibration 80
5.3.4 Capacitive Digital-to-Analog Converter (CDAC) 86
5.4 Experimental Results 97
5.5 Conclusion 100
Chapter 6 System 101
6.1 System Overview 102
6.2 System Specification 103
6.2.1 Image Rejection 103
6.2.2 Two-Tone Third-Order Intermodulation Distortion (IMD3) 107
6.3 Simulation Results 108
6.3.1 Image-Rejection Ratio 108
6.3.2 Linearity and Noise 110
6.3.3 Crosstalk 115
6.4 Experiment Results 117
6.4.1 Operation of Serial-to-Parallel Converter 120
6.4.2 Image Rejection Ration 121
6.4.3 Linearity, Noise and Dynamic Range 123
6.5 Performance Comparison 132
6.6 Conclusion 134
Chapter 7 Conclusion 135
Bibliography 139
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