臺灣博碩士論文加值系統

行動通訊裝置近幾年來進步迅速，且朝向輕薄省電且高頻寬的趨勢發展。為了達成此目的，透過三維整合的寬頻輸出入架構與第四代雙倍資料率同步隨機存取記憶體成為最熱門的技術。本論文著重於兩大行動記憶體的三維整合連結—穿矽連通柱與晶圓級構裝。首先，為了分析穿矽連通柱與矽基板間的基板雜訊耦合，建立了由電阻與電容組成的等效電路，模型中的電阻與電容皆滿足相同的拉普拉斯方程式但具有不同的邊界條件，透過計算不同介質的電容結構可以得到模型中的元件值，並藉由設計接地防護圈結構來驗證其對基板雜訊耦合的抑制效果。
接著，為了處理寬頻輸出入架構晶片間大量穿矽連通柱的問題，本論文基於二維傅立葉轉換提出一種簡化且有效率的週期性穿矽連通柱陣列模型。透過此簡化模型更可以進一步計算寬頻輸出入架構中，降低信號串音的接地穿矽連通柱的位置與數量。
對於另一種三維整合構裝技術，晶圓級構裝，本論文提出一種應用於第四代雙倍資料率同步隨機存取記憶體的新式雙層重新分配層設計，這種新穎的電源接地網格式佈局可以有效提升電源完整度。此外，為了處理製程微縮產生的效應，本文提出二階串聯RLC等效電路與規一化阻抗，並利用適當設計重新分配層的尺寸優化眼圖，使第四代雙倍資料率同步隨機存取記憶體於2微米的晶圓級構裝製程中，可正常運作於4266 Mbps的速度。
最後，除了訊號及電源完整度外，本論文也探討電磁干擾的問題。對於構裝基板中電源接地層的板邊輻射現象，本論文透過模態分析分離不同模態的輻射機制。並設計不同尺寸的接地連通柱以實現不同程度的板邊輻射抑制。

Mobile devices develop rapidly in recent few years, with the trends of the slim, low-power, and high bandwidth features. The three-dimensional integration such as Wide-I/O and LPDDR4 DRAM become the most popular technologies. This dissertation focuses on the interconnects of two popular mobile memories, through-silicon-via (TSV) and wafer-level packaging (WLP). To begin with, the equivalent model consisting of resistors and capacitors is established in order to analyze the substrate noise coupling between TSVs and silicon substrate. It deserves notice that the resistors and capacitors in the equivalent model satisfy the same Laplace equation but with different boundary conditions, and thus the resistance model can be judiciously solved from the capacitance computations which are readily available from commercial software. Based on that, the guard ring design is also employed to validate the accuracy of the present model and its suppressing effect on the substrate noise.
Next, for dealing with large numbers of TSVs between Wide-I/O chips, this dissertation proposed a method of creating a simplified and efficient equivalent model for periodic TSV array based on the two-dimensional Fourier transform. The simplified model is also used to effectively access the position and number of dummy ground TSV to reduce the crosstalk between signals in Wide-I/O architecture.
As for the WLP, this dissertation proposed a novel two-layer re-distributed layer (RDL) design in LPDDR4 applications by utilizing a novel power/ground meshed layout for superior power integrity performance. Besides, in order to handle the effect of process shrinkage, the 2nd order series RLC circuit and normalized resistance is proposed. By adjusting the cross-sectional structure of RDL properly, the eye-diagram can be optimized and LPDDR4 memory can work well at 4266 Mbps on 2 μm WLP.
The last, in addition to signal and power integrity, the dissertation also addressed the electromagnetic interference issues. It employs the mode analysis to separate the radiation mechanisms of different modes for edge radiation of power/ground plane in multi-layer package. The size of shorting via is also designed to implement the different level suppression of edge radiation.

中文摘要 ii
ABSTRACT iv
CONTENTS vi
LIST OF FIGURES ix
LIST OF TABLES xiii
Chapter 1 Introduction 1
1.1 Research Background and Motivation 1
1.2 Literature Survey 5
1.3 Contributions 12
1.4 Organization of the Dissertation 13
Chapter 2 High-Speed DRAM Systems 17
2.1 Double Data Rate DRAM 18
2.2 Development of Mobile DRAM 20
2.2.1 LPDDR4 Memory Technology 20
2.2.2 Wide-I/O Memory Technology 24
2.2.3 Features of Mobile Memory Technologies 29
2.3 Other High-Speed DRAM Technologies 30
Chapter 3 Modeling and Suppression of Substrate Noise in TSV-Based 3-D IC 33
3.1 TSV Technique and Electrical Characteristic 33
3.2 Modeling of Substrate Noise 39
3.3 Parameter Extraction of Substrate Noise Model 44
3.4 Analysis Results and Comparison 46
3.5 Verification and Measurement Results 49
3.6 Summary 54
Chapter 4 Modeling of Through-Silicon-Via Array 55
4.1 Multi-TSV in Wide-I/O Application 56
4.2 Simplified Multi-TSV Model 57
4.3 Extra Ground TSV for Crosstalk Reduction 62
4.4 Summary 66
Chapter 5 Analysis and Design of Signal/Power Integrity for Wafer-Level Packaging 67
5.1 Wafer Level Packaging Technology 67
5.2 Modeling and Analysis of WLP in LPDDR4 70
5.2.1 Modeling for Signal/Power Integrity 72
5.2.2 Equivalent Model for RDL Transmission Line 74
5.2.3 Novel PDN Design of Two-Layer RDL 77
5.3 Design Examples and Simulation Results 81
5.3.1 SI/PI Co-simulation for Two-Layer RDL 81
5.3.2 Effect of Process Scaling on Eye Diagram 83
5.3.3 Optimized Two-Layer RDL of SI/PI Design 84
5.4 Design Procedure for Two-Layer RDL in WLP 85
5.5 Summary 86
Chapter 6 Suppression of Edge Radiation of Multi-Layer Packaging 87
6.1 Edge Radiation and Design of Shorting Vias 88
6.1.1 Edge Radiation of Parallel Power/Ground Planes 89
6.1.2 Mode Mechanism in EMI Suppression 91
6.1.3 Canonical Problem and Closed-form Solution 94
6.1.4 Shorting Vias Design Procedure 99
6.2 Design Examples and Numerical Results 99
6.2.1 Computations of Total Radiated Power 99
6.2.2 Optimal Design for Shorting Vias 102
6.3 Experimental Validation 104
6.4 Summary 106
Chapter 7 Conclusions and Future Works 109
7.1 Conclusions of the Dissertation 109
REFERENCE 111
PUBLICATION LIST 125
ACKNOWLEDGEMENT 127

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